Beam current dependence resulted from nonlinearity and asymmetry of the four channels of digital BPM(Beam Position Monitor) processor deteriorates the BPM performance.A systematic solution based on signal source calib...Beam current dependence resulted from nonlinearity and asymmetry of the four channels of digital BPM(Beam Position Monitor) processor deteriorates the BPM performance.A systematic solution based on signal source calibration tactics has been carried out to rectify this defect.It is optimized for implementation in FPGA.Mathematical illustrations of the calibration method,hardware and software design and implementation are presented.A signal source circuit using frequency synthesis technique is designed as calibration standard.Data acquisition system using JAVA web technology and Ethernet is introduced.Integrated FPGA implementation code architecture is presented,and experimental test results show that the method implemented in FPGA is feasible.Compared to other methods,our approach can rectify the nonlinearity and asymmetry simultaneously.The whole solution is integrated into the DBPM processor and can be executed online.展开更多
This paper presents the design considerations and implementation of a novel topology digital multistage-noise-shaping (MASH) delta-sigma modulator suitable for fractional-N phase-locked-loop (PLL) frequency synthe...This paper presents the design considerations and implementation of a novel topology digital multistage-noise-shaping (MASH) delta-sigma modulator suitable for fractional-N phase-locked-loop (PLL) frequency synthesis. In an effort to reduce the complexity and dissipation,a pipeline technique has been used, and the proposed carry save tree (CST) algorithm optimizes the multi-input adder structure. The circuit has been verified through Matlab simulation, ASIC implementation, and FPGA experiment, which exhibits high performance and potential for a gigahertz range,low-power monolithic CMOS frequency synthesizer.展开更多
Phase modulation is a crucial step when the frequency-based wavefront optimization technique is exploited to measure the optical transmission matrix(TM) of a scattering medium. We report a simple but powerful method, ...Phase modulation is a crucial step when the frequency-based wavefront optimization technique is exploited to measure the optical transmission matrix(TM) of a scattering medium. We report a simple but powerful method, direct digital frequency synthesis(DDS) technology to modulate the phase front of the laser and measure the TM. By judiciously modulating the phase front of a He–Ne laser beam, we experimentally generate a high quality focus at any targeted location through a 2 mm thick 120 grit ground glass diffuser, which is commercially used in laser display and laser holographic display for improving brightness uniformity and reducing speckle. The signal to noise ratio(SNR) of the clear round focus is 50 and the size is about 44 μm. Our study will open up new avenues for enhancing light energy delivery to the optical engine in laser TV to lower the power consumption, phase compensation to reduce the speckle noise, and controlling the lasing threshold in random lasers.展开更多
This paper investigates the design of digital Sigma-Delta Modulator (SDM) for fractional-N frequency synthesizer. Characteristics of SDMs are compared through theory analysis and simulation. The curve of maximum-loop-...This paper investigates the design of digital Sigma-Delta Modulator (SDM) for fractional-N frequency synthesizer. Characteristics of SDMs are compared through theory analysis and simulation. The curve of maximum-loop-bandwidth vs. maximum-phase-noise is suggested to be a new criterion to the performance of SDM,which greatly helps designers to select an appropriate SDM structure to meet their real application requirements and to reduce the cost as low as possible. A low-spur 3-order Mul-tistage Noise Shaping (MASH)-1-1-1 SDM using three 2-bit first-order cascaded modulators is proposed,which balances the requirements of tone-free and maximum operation frequency.展开更多
By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes ...By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes to get an optimum jitter performance and power consumption.For a frequency synthesizer,a large multiple factor prefers PLL based configuration which consumes less power,while a small one needs DLL based topology which produces a better jitter performance.展开更多
In order to solve problems in high dynamic environment, a frequency-locked loop (FLL) assisted phase-locked loop (PLL) is put forward for carrier tracking. On the basis of the analysis of discriminators, the total...In order to solve problems in high dynamic environment, a frequency-locked loop (FLL) assisted phase-locked loop (PLL) is put forward for carrier tracking. On the basis of the analysis of discriminators, the total phase error of the tracking loop is analyzed and a general error expression is derived. By using linearization and Jaffe-Rechtin coefficients, the performance of a special first order FLL-assisted second order PLL is analyzed to get a closed expression. Analysis results and simula- tions show that there exist an optimal FLL loop bandwidth and a optimal PLL loop bandwidth which can make the phase jitter much less than that when the PLL is used alone.展开更多
The static comer frequency and dynamic comer frequency in stochastic synthesis of ground motion from fi- nite-fault modeling are introduced, and conceptual disadvantages of the two are discussed in this paper. Further...The static comer frequency and dynamic comer frequency in stochastic synthesis of ground motion from fi- nite-fault modeling are introduced, and conceptual disadvantages of the two are discussed in this paper. Furthermore, the non-uniform radiation of seismic wave on the fault plane, as well as the trend of the larger rupture area, the lower comer frequency, can be described by the source spectral model developed by the authors. A new dynamic comer frequency can be developed directly from the model. The dependence of ground motion on the size of subfault can be eliminated if this source spectral model is adopted in the synthesis. Finally, the approach presented is validated from the comparison between the synthesized and observed ground motions at six rock stations during the Northridge earthquake in 1994.展开更多
A low phase noise and low spur phase locked loop (PLL) frequency synthesizer for use in global navigation satellite system (GNSS) receivers is proposed. To get a low spur, the symmetrical structure of the phase fr...A low phase noise and low spur phase locked loop (PLL) frequency synthesizer for use in global navigation satellite system (GNSS) receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector (PFD) produces four control signals, which can reach the charge pump (CP) simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.展开更多
The full-bridge converters usually use transformer leakage inductance and parallel resonant capacitors to achieve smooth current commutation and soft switching functions,which can easily cause problems such as energy ...The full-bridge converters usually use transformer leakage inductance and parallel resonant capacitors to achieve smooth current commutation and soft switching functions,which can easily cause problems such as energy leakage and significant duty cycle loss.This paper designs a novel full-bridge zero-current(FB-ZCS)converter with series resonant capacitors and proposes a frequency and phase-shift synthesis modulation(FPSSM)control strategy based on this topology.Compared with the traditional parallel resonant capacitor circuit,the passive components used are significantly reduced,the structure is simple,and there is only a slight energy loss.By controlling the charging time of the capacitor,it can be achieved without additional switches or auxiliary circuits.The automatic control of capacitor energy based on input current addresses the low efficiency of the traditional control strategies.This paper introduces its principle in detail and verifies it through simulation.Finally,an experimental prototype was built further to demonstrate the feasibility of the theory through experiments.The module can be applied to a photovoltaic DC collection system using input parallel output series(IPOS)cascade to provide a new topology for large-scale,long-distance DC transmission.展开更多
An optimized method is presented to design the down scalers in a GHz frequency synthesizer. The down scalers are comprised of dual modulus prescaler (DMP) and programmable & pulse swallow divider,different methods ...An optimized method is presented to design the down scalers in a GHz frequency synthesizer. The down scalers are comprised of dual modulus prescaler (DMP) and programmable & pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively. Using a DMP high speed, lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps. The flexibility and reusability of the progrs, mmable divider is high;its use could be extended to many complicated frequency synthesizers. By comparison,it is a better design on performance of high-frequency circuit and good design flexibility.展开更多
系统地研究了快速跳频PLL中杂散来源,给出了环路杂散模型,定义了杂散抑制比。定性分析了MF SK FH通信系统检测误码率Pe与杂散抑制比λ之间的关系,并通过计算机辅助分析,定量计算出误码率与杂散抑制比的关系曲线。实验结果表明,MFSK FH...系统地研究了快速跳频PLL中杂散来源,给出了环路杂散模型,定义了杂散抑制比。定性分析了MF SK FH通信系统检测误码率Pe与杂散抑制比λ之间的关系,并通过计算机辅助分析,定量计算出误码率与杂散抑制比的关系曲线。实验结果表明,MFSK FH通信系统中存在一个杂散抑制比的最佳设计值,约为-50dB,它为快速跳频PLL的优化设计提供了参考依据。展开更多
基金Supported by the National Natural Science Foundation of China(No.11075198)
文摘Beam current dependence resulted from nonlinearity and asymmetry of the four channels of digital BPM(Beam Position Monitor) processor deteriorates the BPM performance.A systematic solution based on signal source calibration tactics has been carried out to rectify this defect.It is optimized for implementation in FPGA.Mathematical illustrations of the calibration method,hardware and software design and implementation are presented.A signal source circuit using frequency synthesis technique is designed as calibration standard.Data acquisition system using JAVA web technology and Ethernet is introduced.Integrated FPGA implementation code architecture is presented,and experimental test results show that the method implemented in FPGA is feasible.Compared to other methods,our approach can rectify the nonlinearity and asymmetry simultaneously.The whole solution is integrated into the DBPM processor and can be executed online.
文摘This paper presents the design considerations and implementation of a novel topology digital multistage-noise-shaping (MASH) delta-sigma modulator suitable for fractional-N phase-locked-loop (PLL) frequency synthesis. In an effort to reduce the complexity and dissipation,a pipeline technique has been used, and the proposed carry save tree (CST) algorithm optimizes the multi-input adder structure. The circuit has been verified through Matlab simulation, ASIC implementation, and FPGA experiment, which exhibits high performance and potential for a gigahertz range,low-power monolithic CMOS frequency synthesizer.
基金Project supported by the National Key Research and Development Program of China(Grant Nos.2016YFB0401902 and 2016YFB0402001)Key-Area Research and Development Program of Guang Dong Province,China(Grant No.2019B010926001)。
文摘Phase modulation is a crucial step when the frequency-based wavefront optimization technique is exploited to measure the optical transmission matrix(TM) of a scattering medium. We report a simple but powerful method, direct digital frequency synthesis(DDS) technology to modulate the phase front of the laser and measure the TM. By judiciously modulating the phase front of a He–Ne laser beam, we experimentally generate a high quality focus at any targeted location through a 2 mm thick 120 grit ground glass diffuser, which is commercially used in laser display and laser holographic display for improving brightness uniformity and reducing speckle. The signal to noise ratio(SNR) of the clear round focus is 50 and the size is about 44 μm. Our study will open up new avenues for enhancing light energy delivery to the optical engine in laser TV to lower the power consumption, phase compensation to reduce the speckle noise, and controlling the lasing threshold in random lasers.
基金the National Natural Science Foundation of China (No. 60025101, No.90207001, and No. 90307016).
文摘This paper investigates the design of digital Sigma-Delta Modulator (SDM) for fractional-N frequency synthesizer. Characteristics of SDMs are compared through theory analysis and simulation. The curve of maximum-loop-bandwidth vs. maximum-phase-noise is suggested to be a new criterion to the performance of SDM,which greatly helps designers to select an appropriate SDM structure to meet their real application requirements and to reduce the cost as low as possible. A low-spur 3-order Mul-tistage Noise Shaping (MASH)-1-1-1 SDM using three 2-bit first-order cascaded modulators is proposed,which balances the requirements of tone-free and maximum operation frequency.
文摘By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes to get an optimum jitter performance and power consumption.For a frequency synthesizer,a large multiple factor prefers PLL based configuration which consumes less power,while a small one needs DLL based topology which produces a better jitter performance.
文摘In order to solve problems in high dynamic environment, a frequency-locked loop (FLL) assisted phase-locked loop (PLL) is put forward for carrier tracking. On the basis of the analysis of discriminators, the total phase error of the tracking loop is analyzed and a general error expression is derived. By using linearization and Jaffe-Rechtin coefficients, the performance of a special first order FLL-assisted second order PLL is analyzed to get a closed expression. Analysis results and simula- tions show that there exist an optimal FLL loop bandwidth and a optimal PLL loop bandwidth which can make the phase jitter much less than that when the PLL is used alone.
基金supported by National Natural Science Foundation of China under grant No. 50778058 and 90715038National Key Technology Research and Development Program under grant No. 2006BAC13B02
文摘The static comer frequency and dynamic comer frequency in stochastic synthesis of ground motion from fi- nite-fault modeling are introduced, and conceptual disadvantages of the two are discussed in this paper. Furthermore, the non-uniform radiation of seismic wave on the fault plane, as well as the trend of the larger rupture area, the lower comer frequency, can be described by the source spectral model developed by the authors. A new dynamic comer frequency can be developed directly from the model. The dependence of ground motion on the size of subfault can be eliminated if this source spectral model is adopted in the synthesis. Finally, the approach presented is validated from the comparison between the synthesized and observed ground motions at six rock stations during the Northridge earthquake in 1994.
基金supported by the National Natural Science Foundation of China(No.41274047)the Natural Science Foundation of Jiangsu Province(No.BK2012639)+2 种基金the Foundation of Suzhou City(No.SYG201135)the Science and Technology Enterprises in Jiangsu Province Tech-nology Innovation Fund(No.BC2012121)the Changzhou Science and Technology Support Program(Industrial)(No.CE20120074)
文摘A low phase noise and low spur phase locked loop (PLL) frequency synthesizer for use in global navigation satellite system (GNSS) receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector (PFD) produces four control signals, which can reach the charge pump (CP) simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.
基金This work was supported by the Key R&D Program of Tianjin(No.20YFYSGX00060).
文摘The full-bridge converters usually use transformer leakage inductance and parallel resonant capacitors to achieve smooth current commutation and soft switching functions,which can easily cause problems such as energy leakage and significant duty cycle loss.This paper designs a novel full-bridge zero-current(FB-ZCS)converter with series resonant capacitors and proposes a frequency and phase-shift synthesis modulation(FPSSM)control strategy based on this topology.Compared with the traditional parallel resonant capacitor circuit,the passive components used are significantly reduced,the structure is simple,and there is only a slight energy loss.By controlling the charging time of the capacitor,it can be achieved without additional switches or auxiliary circuits.The automatic control of capacitor energy based on input current addresses the low efficiency of the traditional control strategies.This paper introduces its principle in detail and verifies it through simulation.Finally,an experimental prototype was built further to demonstrate the feasibility of the theory through experiments.The module can be applied to a photovoltaic DC collection system using input parallel output series(IPOS)cascade to provide a new topology for large-scale,long-distance DC transmission.
文摘An optimized method is presented to design the down scalers in a GHz frequency synthesizer. The down scalers are comprised of dual modulus prescaler (DMP) and programmable & pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively. Using a DMP high speed, lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps. The flexibility and reusability of the progrs, mmable divider is high;its use could be extended to many complicated frequency synthesizers. By comparison,it is a better design on performance of high-frequency circuit and good design flexibility.
文摘系统地研究了快速跳频PLL中杂散来源,给出了环路杂散模型,定义了杂散抑制比。定性分析了MF SK FH通信系统检测误码率Pe与杂散抑制比λ之间的关系,并通过计算机辅助分析,定量计算出误码率与杂散抑制比的关系曲线。实验结果表明,MFSK FH通信系统中存在一个杂散抑制比的最佳设计值,约为-50dB,它为快速跳频PLL的优化设计提供了参考依据。