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Implementation and integration of a systematic DBPM calibration with PLL frequency synthesis and FPGA 被引量:2
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作者 孙旭东 冷用斌 《Nuclear Science and Techniques》 SCIE CAS CSCD 2014年第2期56-61,共6页
Beam current dependence resulted from nonlinearity and asymmetry of the four channels of digital BPM(Beam Position Monitor) processor deteriorates the BPM performance.A systematic solution based on signal source calib... Beam current dependence resulted from nonlinearity and asymmetry of the four channels of digital BPM(Beam Position Monitor) processor deteriorates the BPM performance.A systematic solution based on signal source calibration tactics has been carried out to rectify this defect.It is optimized for implementation in FPGA.Mathematical illustrations of the calibration method,hardware and software design and implementation are presented.A signal source circuit using frequency synthesis technique is designed as calibration standard.Data acquisition system using JAVA web technology and Ethernet is introduced.Integrated FPGA implementation code architecture is presented,and experimental test results show that the method implemented in FPGA is feasible.Compared to other methods,our approach can rectify the nonlinearity and asymmetry simultaneously.The whole solution is integrated into the DBPM processor and can be executed online. 展开更多
关键词 数据采集系统 频率合成技术 FPGA DBPM 校准方法 集成 pll 光位置检测器
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Analysis and Design of a ΔΣ Modulator for Fractional-N Frequency Synthesis
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作者 张伟超 许俊 +1 位作者 郑增钰 任俊彦 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2006年第1期41-46,共6页
This paper presents the design considerations and implementation of a novel topology digital multistage-noise-shaping (MASH) delta-sigma modulator suitable for fractional-N phase-locked-loop (PLL) frequency synthe... This paper presents the design considerations and implementation of a novel topology digital multistage-noise-shaping (MASH) delta-sigma modulator suitable for fractional-N phase-locked-loop (PLL) frequency synthesis. In an effort to reduce the complexity and dissipation,a pipeline technique has been used, and the proposed carry save tree (CST) algorithm optimizes the multi-input adder structure. The circuit has been verified through Matlab simulation, ASIC implementation, and FPGA experiment, which exhibits high performance and potential for a gigahertz range,low-power monolithic CMOS frequency synthesizer. 展开更多
关键词 △∑ modulator fractional-N frequency synthesis MASH architecture
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Controlling the light wavefront through a scattering medium based on direct digital frequency synthesis technology 被引量:1
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作者 Yuan Yuan Min-Yuan Sun +3 位作者 Yong Bi Wei-Nan Gao Shuo Zhang Wen-Ping Zhang 《Chinese Physics B》 SCIE EI CAS CSCD 2021年第1期283-287,共5页
Phase modulation is a crucial step when the frequency-based wavefront optimization technique is exploited to measure the optical transmission matrix(TM) of a scattering medium. We report a simple but powerful method, ... Phase modulation is a crucial step when the frequency-based wavefront optimization technique is exploited to measure the optical transmission matrix(TM) of a scattering medium. We report a simple but powerful method, direct digital frequency synthesis(DDS) technology to modulate the phase front of the laser and measure the TM. By judiciously modulating the phase front of a He–Ne laser beam, we experimentally generate a high quality focus at any targeted location through a 2 mm thick 120 grit ground glass diffuser, which is commercially used in laser display and laser holographic display for improving brightness uniformity and reducing speckle. The signal to noise ratio(SNR) of the clear round focus is 50 and the size is about 44 μm. Our study will open up new avenues for enhancing light energy delivery to the optical engine in laser TV to lower the power consumption, phase compensation to reduce the speckle noise, and controlling the lasing threshold in random lasers. 展开更多
关键词 optical transmission matrix direct digital frequency synthesis technology phase modulation wavefront optimization
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COMPARISON OF SIGMA-DELTA MODULATOR FOR FRACTIONAL-N PLL FREQUENCY SYNTHESIZER
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作者 Mao Xiaojian Yang Huazhong Wang Hui 《Journal of Electronics(China)》 2007年第3期374-379,共6页
This paper investigates the design of digital Sigma-Delta Modulator (SDM) for fractional-N frequency synthesizer. Characteristics of SDMs are compared through theory analysis and simulation. The curve of maximum-loop-... This paper investigates the design of digital Sigma-Delta Modulator (SDM) for fractional-N frequency synthesizer. Characteristics of SDMs are compared through theory analysis and simulation. The curve of maximum-loop-bandwidth vs. maximum-phase-noise is suggested to be a new criterion to the performance of SDM,which greatly helps designers to select an appropriate SDM structure to meet their real application requirements and to reduce the cost as low as possible. A low-spur 3-order Mul-tistage Noise Shaping (MASH)-1-1-1 SDM using three 2-bit first-order cascaded modulators is proposed,which balances the requirements of tone-free and maximum operation frequency. 展开更多
关键词 FRACTIONAL-N frequency synthesizer Phase Locked Loop pll Sigma-Delta Modulator(SDM)
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一种宽带信号产生的DDS PLL Hybrid新型结构及实现 被引量:4
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作者 赵志勇 常文革 黎向阳 《国防科技大学学报》 EI CAS CSCD 北大核心 2013年第4期103-108,共6页
DDS+PLL Hybrid结构兼顾DDS和PLL的优势,但也兼具DDS和PLL的缺点:宽带信号性能较差;零相位误差跟踪的实现难度大;环路稳定性差;较长的捕获时间;调频斜率受限等。提出了在传统的DDS+PLL Hybrid结构中增加频率扫描电路的方法,能够有效降... DDS+PLL Hybrid结构兼顾DDS和PLL的优势,但也兼具DDS和PLL的缺点:宽带信号性能较差;零相位误差跟踪的实现难度大;环路稳定性差;较长的捕获时间;调频斜率受限等。提出了在传统的DDS+PLL Hybrid结构中增加频率扫描电路的方法,能够有效降低环路设计难度,提高了捕获速度。扫频电路使大带宽、短脉冲的调频信号的产生成为可能。同时提出了预失真相位补偿的方法,极大地提升了信号的脉压性能。设计了实验电路,对所提出的电路结构和相位补偿方法进行了验证。试验结果表明,在环路带宽为1MHz和2MHz时,环路的捕获时间分别减小为2.175μs和1.032μs;相位误差小于4°;信号的脉压性能接近理想,主瓣宽度与理想值相同,PLSR优于-38dB,ISLR优于-9.5dB。 展开更多
关键词 DDS-pll混合结构 宽带 线性扫频 预失真补偿
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The Jitter Performance Comparison Between DLL and PLL-Based RF CMOS Oscillators
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作者 李金城 仇玉林 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2001年第10期1246-1249,共4页
By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes ... By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes to get an optimum jitter performance and power consumption.For a frequency synthesizer,a large multiple factor prefers PLL based configuration which consumes less power,while a small one needs DLL based topology which produces a better jitter performance. 展开更多
关键词 JITTER pll DLL frequency synthesizer RF CMOS transceiver Local Oscillator(LO) Voltage Controlled Delay Line(VCDL) VCO
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Tracking error analysis and simulation of FLL-assisted PLL 被引量:1
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作者 田甜 安建平 张若冰 《Journal of Beijing Institute of Technology》 EI CAS 2012年第4期532-537,共6页
In order to solve problems in high dynamic environment, a frequency-locked loop (FLL) assisted phase-locked loop (PLL) is put forward for carrier tracking. On the basis of the analysis of discriminators, the total... In order to solve problems in high dynamic environment, a frequency-locked loop (FLL) assisted phase-locked loop (PLL) is put forward for carrier tracking. On the basis of the analysis of discriminators, the total phase error of the tracking loop is analyzed and a general error expression is derived. By using linearization and Jaffe-Rechtin coefficients, the performance of a special first order FLL-assisted second order PLL is analyzed to get a closed expression. Analysis results and simula- tions show that there exist an optimal FLL loop bandwidth and a optimal PLL loop bandwidth which can make the phase jitter much less than that when the PLL is used alone. 展开更多
关键词 frequency-locked loop (FLL) assisted phase-locked loop pll phase tracking error Jaffe-Rechtin filter
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基于CCSFF-FPLL的PMSM位置估算误差抑制
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作者 曹江华 苏金章 赵世伟 《微电机》 2024年第8期13-19,37,共8页
在基于滑模观测器的无位置传感器控制系统中,低通滤波器的使用会使反电动势产生相位延迟,在加减速工况下锁相环位置估计的动态性能较差,二者都会造成较大的位置估算误差。针对这两个问题,该文提出了一种基于CCSFF-FPLL的转子位置估算方... 在基于滑模观测器的无位置传感器控制系统中,低通滤波器的使用会使反电动势产生相位延迟,在加减速工况下锁相环位置估计的动态性能较差,二者都会造成较大的位置估算误差。针对这两个问题,该文提出了一种基于CCSFF-FPLL的转子位置估算方法。该方法采用复系数同步频率滤波器(CCSFF)对反电动势进行滤波,利用其在中心频率处没有相位延迟和幅值衰减的特性来实现反电动势的准确提取;同时在传统锁相环的基础上增加了转速前馈的路径,设计了一种前馈锁相环(FPLL)来提取反电动势中的位置信息。仿真与实验结果表明,该文所提的方法能够有效抑制转子位置的估算误差,提高估算精度。 展开更多
关键词 永磁同步电机 位置估算误差抑制 滑模观测器 复系数同步频率滤波器 前馈锁相环
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Dynamic corner frequency in source spectral model for stochastic synthesis of ground motion 被引量:3
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作者 Xiaodan Sun Xiaxin Tao +1 位作者 Guoxin Wang Taojun Liu 《Earthquake Science》 CSCD 2009年第3期271-276,共6页
The static comer frequency and dynamic comer frequency in stochastic synthesis of ground motion from fi- nite-fault modeling are introduced, and conceptual disadvantages of the two are discussed in this paper. Further... The static comer frequency and dynamic comer frequency in stochastic synthesis of ground motion from fi- nite-fault modeling are introduced, and conceptual disadvantages of the two are discussed in this paper. Furthermore, the non-uniform radiation of seismic wave on the fault plane, as well as the trend of the larger rupture area, the lower comer frequency, can be described by the source spectral model developed by the authors. A new dynamic comer frequency can be developed directly from the model. The dependence of ground motion on the size of subfault can be eliminated if this source spectral model is adopted in the synthesis. Finally, the approach presented is validated from the comparison between the synthesized and observed ground motions at six rock stations during the Northridge earthquake in 1994. 展开更多
关键词 source spectral model dynamic corner frequency stochastic synthesis finite-fault
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A low phase noise and low spur PLL frequency synthesizer for GNSS receivers 被引量:1
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作者 李森 江金光 +1 位作者 周细凤 刘江华 《Journal of Semiconductors》 EI CAS CSCD 2014年第1期96-103,共8页
A low phase noise and low spur phase locked loop (PLL) frequency synthesizer for use in global navigation satellite system (GNSS) receivers is proposed. To get a low spur, the symmetrical structure of the phase fr... A low phase noise and low spur phase locked loop (PLL) frequency synthesizer for use in global navigation satellite system (GNSS) receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector (PFD) produces four control signals, which can reach the charge pump (CP) simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc. 展开更多
关键词 pll frequency synthesizer phase noise SPUR PFD CP VCO
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Research on Phase-Shifted Full-Bridge Circuit Based on Frequency and Phase-Shift Synthesis Modulation Strategy
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作者 Mingda Jiang Yanbo Che +2 位作者 Hongfeng Li Muhammad Ishaq Chao Xing 《Energy Engineering》 EI 2022年第2期699-721,共23页
The full-bridge converters usually use transformer leakage inductance and parallel resonant capacitors to achieve smooth current commutation and soft switching functions,which can easily cause problems such as energy ... The full-bridge converters usually use transformer leakage inductance and parallel resonant capacitors to achieve smooth current commutation and soft switching functions,which can easily cause problems such as energy leakage and significant duty cycle loss.This paper designs a novel full-bridge zero-current(FB-ZCS)converter with series resonant capacitors and proposes a frequency and phase-shift synthesis modulation(FPSSM)control strategy based on this topology.Compared with the traditional parallel resonant capacitor circuit,the passive components used are significantly reduced,the structure is simple,and there is only a slight energy loss.By controlling the charging time of the capacitor,it can be achieved without additional switches or auxiliary circuits.The automatic control of capacitor energy based on input current addresses the low efficiency of the traditional control strategies.This paper introduces its principle in detail and verifies it through simulation.Finally,an experimental prototype was built further to demonstrate the feasibility of the theory through experiments.The module can be applied to a photovoltaic DC collection system using input parallel output series(IPOS)cascade to provide a new topology for large-scale,long-distance DC transmission. 展开更多
关键词 Full-bridge converter frequency and phase-shift synthesis modulation(FPSSM) photovoltaic DC collection system control strategy
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基于DDS+PLL的频率合成方法研究
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作者 王锋 郭中会 +2 位作者 庞洋 张一萌 陈鹏 《环境技术》 2024年第4期155-159,共5页
针对传统的PLL在小数分频时引起的边界杂散问题,采用DDS作为PLL的参考时钟,通过动态调整DDS的输出频率及PLL的整数分频比,使PLL在整数分频模式下仍具有小步进的合成频率精度。经过理论分析和实测实验验证了方案的可行性,实测实验表明,采... 针对传统的PLL在小数分频时引起的边界杂散问题,采用DDS作为PLL的参考时钟,通过动态调整DDS的输出频率及PLL的整数分频比,使PLL在整数分频模式下仍具有小步进的合成频率精度。经过理论分析和实测实验验证了方案的可行性,实测实验表明,采用DDS+PLL方案合成频率可以有效解决整数边界杂散,并实现了最大9.31 Hz的频率步进精度。 展开更多
关键词 小数分频 边界杂散 DDS激励pll 小步进 频率精度
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基于DDS+PLL技术频率合成器的设计与实现 被引量:29
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作者 陈科 叶建芳 马三涵 《国外电子测量技术》 2010年第4期43-47,共5页
本文介绍了DDS+PLL方式实现频率合成的基本原理和技术优势。根据GSM-1900系统对频率源的要求,提出了一种基于DDS+PLL结构频率合成器的硬件电路设计方案。借助于EDA仿真软件ADS、ADISimPLL完成了频率合成器中关键模块参数的确定,并对系... 本文介绍了DDS+PLL方式实现频率合成的基本原理和技术优势。根据GSM-1900系统对频率源的要求,提出了一种基于DDS+PLL结构频率合成器的硬件电路设计方案。借助于EDA仿真软件ADS、ADISimPLL完成了频率合成器中关键模块参数的确定,并对系统性能进行了仿真分析,最后运用AD9851、ADF4113等芯片完成了频率合成器的硬件实现,测量结果表明该频率合成器达到了设计指标,系统性能良好。 展开更多
关键词 DDS pll 频率合成
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基于DDS与PLL混合的频率合成改进方法研究 被引量:7
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作者 王锋 刘鹏远 李兵 《微电子学与计算机》 CSCD 北大核心 2017年第5期17-20,共4页
电子系统对频率源的精度、频率分辨率、转换时间和频谱纯度等指标提出了越来越高的要求.锁相频率合成技术具有体积小、电路简洁、杂散抑制度高,具有窄带跟踪滤波能力的特点,得到了广泛应用,但其存在频率步进与转换时间的相互制约的缺点.... 电子系统对频率源的精度、频率分辨率、转换时间和频谱纯度等指标提出了越来越高的要求.锁相频率合成技术具有体积小、电路简洁、杂散抑制度高,具有窄带跟踪滤波能力的特点,得到了广泛应用,但其存在频率步进与转换时间的相互制约的缺点.而DDS具有极高的分辨率,极快的频率转换速度,输出频率上限不高.两种常用的方法有各自的优势和不足,因此可以采用DDS+PLL技术方案,既能保持锁相环路的优点,又弥补了锁相环路的不足.本文正是基于这一思想提出了混合频率合成方法的改进方案. 展开更多
关键词 DDS pll 频率合成 转换时间
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一种DDS/PLL混合型高分辨率频率合成器 被引量:7
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作者 王建新 刘国岁 朱伟强 《电子测量与仪器学报》 CSCD 1999年第4期72-75,共4页
本文利用直接数字频率合成器频率分辨率高和相位噪声低而锁相环频率合成器输出频率高和对鉴相输入呈现窄带特性的优点,用STEL一1175DDS芯片设计了一个高分辨率正弦信号产生器,并以此推动锁相环进行倍频。通过这种 DDS... 本文利用直接数字频率合成器频率分辨率高和相位噪声低而锁相环频率合成器输出频率高和对鉴相输入呈现窄带特性的优点,用STEL一1175DDS芯片设计了一个高分辨率正弦信号产生器,并以此推动锁相环进行倍频。通过这种 DDS/PLL混合型频率合成器,得到了中心频率为 38MHz的高分辨率正弦信号。本文给出了电路设计过程及测试结果。 展开更多
关键词 锁相环 频率合成器 DDFS 混合型 正弦信号
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Design of Down Scalers in Mixed-Signal GHz Frequency Synthesizer 被引量:1
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作者 徐勇 王志功 +3 位作者 仇应华 李智群 胡庆生 闵锐 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2005年第9期1711-1715,共5页
An optimized method is presented to design the down scalers in a GHz frequency synthesizer. The down scalers are comprised of dual modulus prescaler (DMP) and programmable & pulse swallow divider,different methods ... An optimized method is presented to design the down scalers in a GHz frequency synthesizer. The down scalers are comprised of dual modulus prescaler (DMP) and programmable & pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively. Using a DMP high speed, lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps. The flexibility and reusability of the progrs, mmable divider is high;its use could be extended to many complicated frequency synthesizers. By comparison,it is a better design on performance of high-frequency circuit and good design flexibility. 展开更多
关键词 pll frequency synthesizer dual-modulus prescaler PROGRAMMABLE pulse swallow divider
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快速跳频PLL中杂散抑制比的最佳设计值 被引量:2
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作者 夏定元 王卫东 郑继禹 《系统工程与电子技术》 EI CSCD 北大核心 2004年第1期11-13,29,共4页
系统地研究了快速跳频PLL中杂散来源,给出了环路杂散模型,定义了杂散抑制比。定性分析了MF SK FH通信系统检测误码率Pe与杂散抑制比λ之间的关系,并通过计算机辅助分析,定量计算出误码率与杂散抑制比的关系曲线。实验结果表明,MFSK FH... 系统地研究了快速跳频PLL中杂散来源,给出了环路杂散模型,定义了杂散抑制比。定性分析了MF SK FH通信系统检测误码率Pe与杂散抑制比λ之间的关系,并通过计算机辅助分析,定量计算出误码率与杂散抑制比的关系曲线。实验结果表明,MFSK FH通信系统中存在一个杂散抑制比的最佳设计值,约为-50dB,它为快速跳频PLL的优化设计提供了参考依据。 展开更多
关键词 跳频通信 频率合成 锁相环 杂散抑制比
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采用DDS+PLL技术实现S波段频率合成的一种方法 被引量:14
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作者 杨国渝 粟显义 《电子科技大学学报》 EI CAS CSCD 北大核心 1999年第4期388-391,共4页
分析了现有的DDS 与PLL 混合电路方案实现频率合成的优缺点,提出了一种用DDS 与PLL 混合电路实现S 波段频率合成的新方法。给出了一个示例,并用CAD
关键词 频率合成 锁相环 DDS pll 直接数字合成 混合法
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PLL驱动DDS的低相噪小步进LFM信号源设计 被引量:4
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作者 王文才 陈昌明 黄刚 《电子器件》 CAS 北大核心 2015年第2期348-351,共4页
介绍了一种低相噪线性调频(LFM)雷达信号源的产生和实现方案。通过分析DDS输出信号频谱和杂散,采用HMC704控制VCO的方法设计了1 GHz的锁相环路(PLL)作为DDS的时钟驱动电路,并对环路滤波器和AD9910硬件电路优化设计改善杂散和相噪性能。... 介绍了一种低相噪线性调频(LFM)雷达信号源的产生和实现方案。通过分析DDS输出信号频谱和杂散,采用HMC704控制VCO的方法设计了1 GHz的锁相环路(PLL)作为DDS的时钟驱动电路,并对环路滤波器和AD9910硬件电路优化设计改善杂散和相噪性能。通过计算寄存器参数和分析SPI总线时序,利用FPGA对DDS和PLL高速配置。最后给出了系统实物图和测试方法,实测结果表明:该线性调频源输出幅度大于-3dBm,频率步进为1kHz,相位噪声优于-103dBc/Hz@1kHz,各项指标满足实际工程要求。 展开更多
关键词 频率源 线性调频 pll+DDS(锁相环-直接数字系统) AD9910 HMC704
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基于HDMI视频信号接收的电荷泵PLL设计 被引量:2
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作者 肖剑 李冬仓 +1 位作者 孙硕 张福甲 《西安石油大学学报(自然科学版)》 CAS 2007年第6期96-100,共5页
介绍了一种实现HDMI中数字视频信号接收的方法,设计并实现了一种新的用于HDMI中像素数据和时钟信号恢复的电荷泵锁相环;通过V-I电路的改进降低了压控震荡器的增益,改善了控制电压的波动对压控震荡器频率的影响,从而减小时钟抖动;采用频... 介绍了一种实现HDMI中数字视频信号接收的方法,设计并实现了一种新的用于HDMI中像素数据和时钟信号恢复的电荷泵锁相环;通过V-I电路的改进降低了压控震荡器的增益,改善了控制电压的波动对压控震荡器频率的影响,从而减小时钟抖动;采用频率检测电路对输入时钟信号频率进行自动检测分段,可实现大的频率捕获范围,从而实现了对高达UXGA格式的数字视频信号接收;采用Hspice-RF工具对压控震荡器的抖动和相位噪声性能进行仿真,SMIC0.18μsCMOS混合信号工艺进行了流片验证,测试结果表明输入最大1.65Gbit/s像素数据信号条件下PLL输出的时钟信号抖动小于200ps. 展开更多
关键词 高清晰度多媒体接口(HDMI) 锁相环 频率捕获 过采样
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