A low phase noise and low spur phase locked loop （PLL） frequency synthesizer for use in global navigation satellite system （GNSS） receivers is proposed. To get a low spur, the symmetrical structure of the phase fr...A low phase noise and low spur phase locked loop （PLL） frequency synthesizer for use in global navigation satellite system （GNSS） receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector （PFD） produces four control signals, which can reach the charge pump （CP） simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.展开更多
A wide-band frequency synthesizer with low phase noise is presented.The frequency tuning range is from 474 to 858 MHz which is compatible with U-band CMMB application while the S-band frequency is also included. Three...A wide-band frequency synthesizer with low phase noise is presented.The frequency tuning range is from 474 to 858 MHz which is compatible with U-band CMMB application while the S-band frequency is also included. Three VCOs with selectable sub-band are integrated on chip to cover the target frequency range.This PLL is fabricated with 0.35μm SiGe BiCMOS technology.The measured result shows that the RMS phase error is less than 1°and the reference spur is less than -60 dBc.The proposed PLL consumes 20 mA current from a 2.8 V supply.The silicon area occupied without PADs is 1.17 mm;.展开更多
This paper presents a low phase-noise fractional-N frequency synthesizer which provides an inphase/quadrature-phase（I/Q） signal over a frequency range of 220–1100 MHz for wireless networks of industrial automation...This paper presents a low phase-noise fractional-N frequency synthesizer which provides an inphase/quadrature-phase（I/Q） signal over a frequency range of 220–1100 MHz for wireless networks of industrial automation（WIA） applications. Two techniques are proposed to achieve the wide range. First, a 1.4–2.2 GHz ultralow gain voltage-controlled oscillator（VCO） is adopted by using 128 tuning curves. Second, a selectable I/Q divider is employed to divide the VCO frequency by 2 or 3 or 4 or 6. Besides, a phase-switching prescaler is proposed to lower PLL phase noise, a self-calibrated charge pump is used to suppress spur, and a detect-boosting phase frequency detector is adopted to shorten settling time. With a 200 k Hz loop bandwidth, lowest measured phase noise is 106 dBc/Hz at a 10 k Hz offset and 131 dBc/Hz at a 1 MHz offset. Fabricated in the TSMC 0.18 μm CMOS process, the synthesizer occupies a chip area of 1.2 mm^2, consumes only 15 m W from the 1.8 V power supply,and settles within 13.2 s. The synthesizer is optimized for the WIA applications, but can also be used for other short-range wireless communications, such as 433, 868, 916 MHz ISM band applications.展开更多
高性能的频率综合器会直接影响到雷达、通信、遥测遥控、电子对抗等电子系统的性能,其主要技术指标包括低相噪、低杂散、小步进、宽频带等.本文基于某工程的实际需求,根据锁相合成技术,采用HMC983+HMC984套片研制了一款S频段步进为100 H...高性能的频率综合器会直接影响到雷达、通信、遥测遥控、电子对抗等电子系统的性能,其主要技术指标包括低相噪、低杂散、小步进、宽频带等.本文基于某工程的实际需求,根据锁相合成技术,采用HMC983+HMC984套片研制了一款S频段步进为100 Hz的频率综合器,针对设计中小数分频杂散较高的特点,提出了一种可变参考频率的方案,通过避开鉴相频率的整数点有效降低了小数分频中的杂散,同时,鉴相频率的提高使得N值降低,相位噪声恶化减小.测试结果表明,随着鉴相频率的提高,值降低,相位噪声恶化减小,样机杂散指标最差点为72 d Bc.展开更多
基金supported by the National Natural Science Foundation of China(No.41274047)the Natural Science Foundation of Jiangsu Province(No.BK2012639)+2 种基金the Foundation of Suzhou City(No.SYG201135)the Science and Technology Enterprises in Jiangsu Province Tech-nology Innovation Fund(No.BC2012121)the Changzhou Science and Technology Support Program(Industrial)(No.CE20120074)
文摘A low phase noise and low spur phase locked loop （PLL） frequency synthesizer for use in global navigation satellite system （GNSS） receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector （PFD） produces four control signals, which can reach the charge pump （CP） simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.
文摘A wide-band frequency synthesizer with low phase noise is presented.The frequency tuning range is from 474 to 858 MHz which is compatible with U-band CMMB application while the S-band frequency is also included. Three VCOs with selectable sub-band are integrated on chip to cover the target frequency range.This PLL is fabricated with 0.35μm SiGe BiCMOS technology.The measured result shows that the RMS phase error is less than 1°and the reference spur is less than -60 dBc.The proposed PLL consumes 20 mA current from a 2.8 V supply.The silicon area occupied without PADs is 1.17 mm;.
基金supported by the National High Technology Research and Development Program of China(No.2011AA040102)
文摘This paper presents a low phase-noise fractional-N frequency synthesizer which provides an inphase/quadrature-phase（I/Q） signal over a frequency range of 220–1100 MHz for wireless networks of industrial automation（WIA） applications. Two techniques are proposed to achieve the wide range. First, a 1.4–2.2 GHz ultralow gain voltage-controlled oscillator（VCO） is adopted by using 128 tuning curves. Second, a selectable I/Q divider is employed to divide the VCO frequency by 2 or 3 or 4 or 6. Besides, a phase-switching prescaler is proposed to lower PLL phase noise, a self-calibrated charge pump is used to suppress spur, and a detect-boosting phase frequency detector is adopted to shorten settling time. With a 200 k Hz loop bandwidth, lowest measured phase noise is 106 dBc/Hz at a 10 k Hz offset and 131 dBc/Hz at a 1 MHz offset. Fabricated in the TSMC 0.18 μm CMOS process, the synthesizer occupies a chip area of 1.2 mm^2, consumes only 15 m W from the 1.8 V power supply,and settles within 13.2 s. The synthesizer is optimized for the WIA applications, but can also be used for other short-range wireless communications, such as 433, 868, 916 MHz ISM band applications.
文摘高性能的频率综合器会直接影响到雷达、通信、遥测遥控、电子对抗等电子系统的性能,其主要技术指标包括低相噪、低杂散、小步进、宽频带等.本文基于某工程的实际需求,根据锁相合成技术,采用HMC983+HMC984套片研制了一款S频段步进为100 Hz的频率综合器,针对设计中小数分频杂散较高的特点,提出了一种可变参考频率的方案,通过避开鉴相频率的整数点有效降低了小数分频中的杂散,同时,鉴相频率的提高使得N值降低,相位噪声恶化减小.测试结果表明,随着鉴相频率的提高,值降低,相位噪声恶化减小,样机杂散指标最差点为72 d Bc.
