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A 10 Gb/s burst-mode clock and data recovery circuit
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作者 顾皋蔚 朱恩 +1 位作者 林叶 刘文松 《Journal of Semiconductors》 EI CAS CSCD 2012年第7期126-130,共5页
We introduce a gated oscillator based on XONR/XOR cells and illustrate its working process. A halfrate BM-CDR circuit based on the proposed oscillator is designed, and the design is implemented in SMIC 0.13 μm CMOS t... We introduce a gated oscillator based on XONR/XOR cells and illustrate its working process. A halfrate BM-CDR circuit based on the proposed oscillator is designed, and the design is implemented in SMIC 0.13 μm CMOS technology occupying an area of 675 ×25 μm2. The measured results show that this circuit can recover clock and data from each 10 Gbit/s burst-mode data packet within 5 bits, and the recovered data pass eye-mask test defined in IEEE standard 802.3av. 展开更多
关键词 IOG-EPON clock and data recovery BURST-MODE gated voltage-controlled-oscillator frequencylocked loop
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