Readout electronics for a high-resolution soft X-ray spectrometer based on silicon drift detector

The readout electronics for a prototype soft X-ray spectrometer based on silicon drift detector(SDD),for precisely measuring the energy and arrival time of X-ray photons is presented in this paper.The system mainly consists of two parts,i.e.,an analog electronics section(including a pre-amplifier,a signal shaper and filter,a constant fraction timing circuit,and a peak hold circuit)and a digital electronics section(including an ADC and a TDC).Test results with X-ray sources show that an energy dynamic range of 1-10 keV with an integral nonlinearity of less than 0.1%can be achieved,and the energy resolution is better than 160 eV @ 5.9 keV FWHM.Using a waveform generator,test results also indicate that time resolution of the electronics system is about 3.7 ns,which is much less than the transit time spread of SDD(<100 ns)and satisfies the requirements of future applications.

Prototype of the readout electronics for the RICH PID detector in the STCF

The ring imaging Cherenkov(RICH) detector for particle identification(PID) is being evaluated for the future super tau-charm facility(STCF) complex. In this work, the prototype readout electronics for the RICH PID detector is designed. The prototype RICH PID detector is based on a thick gas electron multiplier combined with a micromegas detector for Cherenkov light detection. Considering that there will be a large number(~ 690,000) of detector channels in future RICH detector, the readout electronics faces many challenges to precisely measuring time and charge information, such as reducing the noise,increasing density, and improving precision. The requirements of the readout electronics are explored, the downselection of the ASICs is made and thus a prototype readout electronics is designed and implemented. Tests are also conducted to evaluate the performance of the prototype readout electronics, and the results indicate that the time resolution is better than ~ 1 ns(RMS) when the input charge is greater than ~ 12 fC based on the APV25chip, while the time resolution is better than ~ 1 ns(RMS) at an input charge of over ~ 48 fC based on the AGET and STCF ASIC chips, and the equivalent noise charge is better than ~ 0.5 fC(RMS) @ 20 pF based on the three ASICs. The test results indicate that the prototype readout electronics design meets the requirement of the future RICH PID detector and thus provides a reference for future engineering.

Design and development of multi-channel front end electronics based on dual-polarity charge-to-digital converter for SiPM detector applications

With the development of silicon photomultiplier(SiPM)technology,front-end electronics for SiPM signal processing have been highly sought after in various fields.A compact 64-channel front-end electronics(FEE)system achieved by fieldprogrammable gate array-based charge-to-digital converter(FPGA-QDC)technology was built and developed.The FEE consists of an analog board and FPGA board.The analog board incorporates commercial amplifiers,resistors,and capacitors.The FPGA board is composed of a low-cost FPGA.The electronics performance of the FEE was evaluated in terms of noise,linearity,and uniformity.A positron emission tomography(PET)detector with three different readout configurations was designed to validate the readout capability of the FEE for SiPM-based detectors.The PET detector was made of a 15×15 lutetium–yttrium oxyorthosilicate(LYSO)crystal array directly coupled with a SiPM array detector.The experimental results show that FEE can process dual-polarity charge signals from the SiPM detectors.In addition,it shows a good energy resolution for 511-keV gamma photons under the dual-end readout for the LYSO crystal array irradiated by a Na-22 source.Overall,the FEE based on FPGA-QDC shows promise for application in SiPM-based radiation detectors.

Design of a Low-Noise Front-End Readout Circuit for CdZnTe Detectors

In this paper, the design of a novel low-noise front-end readout circuit for Cadmium zinc telluride (CdZnTe) X-ray and γ-ray detectors is described. The front-end readout circuits include the charge sensitive amplifier (CSA) and the CR-RC shaper is implemented in TSMC 0.35 μm mixed-signal CMOS technology. The die size of the prototype chip is 4.9 mm × 2.2 mm. The simulation results show that, the noise performance is 46 electrons + 10 electrons/pF, and power consumption is 1.65 mW per channel.

Design of a Novel Front-End Readout ASIC for PET Imaging System

The architecture of a multi-channel front-end system is important for realizing a high-resolution PET system. We propose a novel front-end readout electronic system with TDC to deal with time information for PET system which can easily design the timing control. Each channel consists of a charge preamplifier, slow/fast shaper, discriminator and an analog memory. There are an ADC and a TDC to process the energy information and time information for each channel at the same time. In this paper, the whole system signals flow is all simulated by MATLAB. The simulation results show that the proposed system can process slender current from the detector and achieve the energy and time information. The proposed architecture can be applied to high-resolution PET imaging systems with multi-channel ASICs.

Low-power SiPM readout BETA ASIC for space applications

The BETA application-specific integrated circuit(ASIC)is a fully programmable chip designed to amplify,shape and digitize the signal of up to 64 Silicon photomultiplier(SiPM)channels,with a power consumption of approximately~1 mW/channel.Owing to its dual-path gain,the BETA chip is capable of resolving single photoelectrons(phes)with a signal-to-noise ratio(SNR)>5 while simultaneously achieving a dynamic range of~4000 phes.Thus,BETA can provide a cost-effective solution for the readout of SiPMs in space missions and other applications with a maximum rate below 10 kHz.In this study,we describe the key characteristics of the BETA ASIC and present an evaluation of the performance of its 16-channel version,which is implemented using 130 nm technology.The ASIC also contains two discriminators that can provide trigger signals with a time jitter down to 400 ps FWHM for 10 phes.The linearity error of the charge gain measurement was less than 2%for a dynamic range as large as 15 bits.

Development of front-end readout electronics for silicon strip detectors

Front-end readout electronics have been developed for silicon strip detectors at our institute. In this system an Application Specific Integrated Circuit （ASIC） ATHED is used to realize multi-channel energy and time measurements. The slow control of ASIC chips is achieved by parallel port and the timing control signals of ASIC chips are implemented with the CPLD. The data acquisition is carried out with a PXI-DAQ card. The software has a user-friendly GUI developed with LabWindows/CVI in the Windows XP operating system. The test results show that the energy resolution is about 1.14% for alpha at 5.48 MeV and the maximum channel crosstalk of the system is 4.60%. The performance of the system is very reliable and is suitable for nuclear physics experiments.

A 5.12-GHz LC-based phase-locked loop for silicon pixel readouts of high-energy physics

There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.

Design of a high-dynamic-range prototype readout system for VLAST calorimeter

In the future, the Very Large Area gamma-ray Space Telescope is expected to observe high-energy electrons and gamma rays in the MeV to TeV range with unprecedented acceptance. As part of the detector suite, a high-energy imaging calorimeter(HEIC) is currently being developed as a homogeneous calorimeter that utilizes long bismuth germanate(BGO) scintillation crystals as both absorbers and detectors. To accurately measure the energy deposition in the BGO bar of HEIC, a highdynamic-range readout method using a silicon photomultiplier(SiPM) and multiphotodiode(PD) with different active areas has been proposed. A prototype readout system that adopts multichannel charge measurement ASICs was also developed to read out the combined system of SiPMs and PDs. Preliminary tests confirmed the feasibility of the readout scheme, which is expected to have a dynamic range close to 10~6.

Design of the readout electronics for the DAMPE Silicon Tracker detector

The Silicon Tracker （STK） is one of the detectors of the DAMPE satellite used to measure the incidence direction of high energy cosmic rays. It consists of 6 X-Y double layers of silicon micro-strip detectors with 73728 readout channels. It is a great challenge to read out the channels and process the huge volume of data in the harsh environment of space. 1152 Application Specific Integrated Circuits （ASIC） and 384 ADCs are used to read out the detector channels. 192 Tracker Front-end Hybrid （TFH） modules and 8 identical Tracker Readout Board （TRB） modules are designed to control and digitalize the front signals. In this paper, the design of the readout electronics for the STK and its performance are presented in detail.

Design of fast adaptive readout system for wire scanners

A new wide-range fast readout system capable of adaptive identification is designed for wire scanners,which are used to measure beam profiles and emittance.This system is capable of handling varying current signals with Gaussian distributions and current pulses up to 1000 counts/s, as well as an input current range of 1 n A–1 m A. When tested, the resolution was found to exceed 3.68% for full scale, the nonlinearity was found to be less than 0.11%, and the measurement sensibility was found to be less than 5 p A. We believe that the system will play a crucial role in improving the measurement accuracy of beam diagnosis and the efficiency of accelerator operation,as well as decreasing the time required for beam tuning.This system was applied to the beam diagnosis of an injector II prototype for an accelerator-driven subcritical system and produced excellent measurement results. A description of the adaptive fast readout system for wire scanners is presented in this paper.

Design and development of compact readout electronics with silicon photomultiplier array for a compact imaging detector

This work aims at developing compact readout electronics for a compact imaging detector module with silicon photomultiplier （SPM） array. The detector module consists of a LYSO crystal array coupling with a SensL’s 4×4 SPM array. A compact multiplexed readout based on a discretized positioning circuit （DPC） was developed to reduce the readout channels from 16 to 4 outputs. Different LYSO crystal arrays of 4×4, 8×8 and 12×12 with pixel sizes of 3.2, 1.6 and 1.0 mm respectively, have been tested with the compact readout board using a 137 Cs source. The initial results show that the compact imaging detector module with the compact multiplexed readout could clearly resolve 1 mm×1 mm×10 mm LYSO scintillation crystal array except those at the edges. The detector’s intrinsic spatial resolution up to 1 mm can be achieved with the 3 mm×3 mm size SPMArray4 through light sharing and compact multiplexed readout. Our results indicate that this detector module is feasible for the development of high-resolution compact PET.

基于电流放大芯片的Micromegas探测器高集成度读出电子学设计

高分辨、大面积Micromegas探测器广泛应用于粒子物理实验、医学成像和工业检测等领域。针对Micromegas探测器多通道的读出需求,设计并实现了一种512通道的高集成度前端电子学(compact frontend electronics,Compact_FEC)。该电子学采用电流读出芯片ADAS1128,芯片集成128个电流放大器,可实现多通道电荷信息测量。电子学支持USB3.0和千兆以太网通信,可实现与上位机进行通讯交互。通过对电子学性能进行测试,在电子学线性动态范围为−77.97~0 fC的测试条件下,增益约213.6 Code/fC,积分非线性为2.7%,噪声小于0.7 fC。为验证读出电子学对Micromegas探测器阳极条信号的读出能力,利用^(55)Fe放射源进行X射线能量分辨率测试,同时利用宇宙射线进行缪子击中位置重建位置分辨率测试。通过放射源测试可探测到X射线的全能峰与Ar逃逸峰;其中全能峰能量分辨率约20.23%@5.9 keV,全能峰与逃逸峰峰值比约2.09∶1。缪子击中位置测试结果表明,读出电子学测得Micromegas探测器x维度和y维度的位置分辨率分别为0.240 mm和0.243 mm。上述两项测试验证了Compact_FEC在单粒子测量模式下可用于读出Micromegas探测器。

基于运算放大器的超导纳米线单光子探测器低温直流耦合读出电路

超导纳米线单光子探测器(SNSPD)具有高计数率、高探测效率和低暗计数等优点,在光量子通信、光量子计算、激光测距与成像等领域发挥着重要作用.SNSPD的最大计数率(探测速度)会受前级读出电路的影响,为了提升最大计数率,通常需要使用一个宽带宽的低温直流耦合读出电路.本文报道了基于商用高速运算放大芯片OPA855搭建的SNSPD低温直流耦合放大读出电路,系统表征了该电路从室温300 K到低温4.2 K下的性能参数.通过提升OPA855的工作电压,解决了电路在低温下带宽损失的问题.进一步,将OPA855放大电路安装在40 K温区,使用其实现了SNSPD探测性能的实验评估.相对于常规室温交流耦合电路,SNSPD的最大计数率约提升了1.3倍.本研究可为OPA855芯片在高速SNSPD等低温领域提供相关参考信息.

基于自研ASIC芯片HEPS中硅微条探测器读出电子学原型系统设计与测试

时间分辨X射线粉末衍射技术是探测物质晶体结构及其演变的重要手段。单光子计数型硅微条探测器因其灵敏度高和死时间低,在高能同步辐射光源(HEPS)的X射线粉末衍射实验中发挥着重要作用。研制适用于单光子计数型一维硅微条探测器的专用ASIC读出芯片(SSDROC)及其读出电子学系统,并采用一种新标定方法解决了SSDROC各通道对同一输入输出响应不一致的问题,该方法可显著提高各通道数据一致性并减小衍射实验数据的统计误差。探测器完成各项性能测试,结果表明整体系统线性优秀、能量分辨能力强、噪声低以及计数率高,为将来大覆盖角度一维硅微条探测器系统研制奠定坚实基础。

高计数率多通道时间测量与串行读出电路研制

近年来应用于中高能核物理实验的先进前端读出专用集成电路(application specific integrated circuit,ASIC)芯片呈现出越来越强的数字化趋势,可提高系统的集成度并降低功耗。论文研制了一种高计数率多通道时间测量与串行读出电路(high-count rate multi-channel time measurement and serial readout circuit,HMTRC),可实现核事件去稀疏化、去随机化的读出。该电路主要包括了基于时钟分相技术的时间数字转化器、控制器、先进先出存储器和基于令牌环逻辑的轮询读出模块。HMTRC已被集成到一款自研的16通道前端读出ASIC芯片中,可测量和储存时间信息,并利用数字驱动的前端读出架构实现时间与能量信息同步读出。测试表明,时间分辨率好于2 ns,功能符合预期。

面向行星表面元素测量的小型化伽马谱仪原理样机设计

对行星表面物质受宇宙射线激发或天然衰变而产生的伽马射线进行探测,是一种测量行星表面主要元素成分及其空间分布的可靠技术手段,已被多个行星探测任务采用。提出了将CZT探测器与SiPM读出闪烁晶体相结合的行星元素伽马谱仪方案,该方案兼具低能段的高能量分辨率和高能段的高探测效率,同时可以减小来自非探测方向伽马背景的影响,且具有较小的体积、重量和功耗。为进行初步的技术路线验证,设计了一个将CZT阵列(单个灵敏尺寸1 cm×1 cm×0.5 cm)与BGO探测器(晶体的主体尺寸8.4 cm×8.4 cm×4 cm)相结合的小型化伽马谱仪原理样机,并开展了物理模拟。完成了前端探测器模块、数据处理模块和FPGA控制逻辑的设计实现,以及原理样机的组装。使用放射源、上海光源激光伽马光束线和中子激发伽马对谱仪进行了测试,CZT探测器对^(137)Cs@662 keV伽马射线的能量分辨率(FWHM)为2.1%,可以较好地分辨低能伽马射线,BGO晶体能够较好地探测和分辨高能伽马射线。该方案为未来小型化行星伽马谱仪的工程设计提供了参考。

Clock distribution for BaF2 readout electronics at CSNS-WNS

A BaF2（Barium Fluoride） detector array is designed to precisely measure the（n, γ） cross section at the CSNS-WNS（white neutron source at China Spallation Neutron Source）. It is a 4π solid angle-shaped detector array consisting of 92 BaF2 crystal elements. To discriminate signals from the BaF2 detector, a pulse shape discrimination method is used, supported by a waveform digitization technique. There are 92 channels for digitizing. The precision and synchronization of clock distribution restricts the performance of waveform digitizing. In this paper, a clock prototype for the BaF2 readout electronics at CSNS-WNS is introduced. It is based on the PXIe platform and has a twin-stage tree topology. In the first stage, clock is synchronously distributed from the tree root to each PXIe crate through a coaxial cable over a long distance, while in the second stage, the clock is further distributed to each electronic module through a PXIe dedicated differential star bus. With the help of this topology, each tree node can fan out up to 20 clocks with 3U size. Test results show the clock jitter is less than 20 ps, which meets the requirements of the BaF2 readout electronics. Besides, this clock system has the advantages of high density, simplicity, scalability and cost saving, so it can be useful for other clock distribution applications.

核电子学在空间科学探测领域的应用

21世纪以来,随着科学技术的进步和对宇宙探索的不懈追求,我国成功发射了多颗空间科学卫星和深空探测载荷。在这些空间科学卫星或搭载的科学仪器中,核与粒子探测器发挥着至关重要的作用。核电子学作为探测器的重要组成部分,其功能涵盖前端信号放大读出、数字化、触发判选与处理等多个环节。空间科学探测中的核电子学除满足探测器在高分辨率、大动态范围、精确粒子鉴别和数据压缩等方面的需求,同时还须符合空间环境下的抗辐照、高可靠性和长寿命等工程要求。本文通过回顾核电子学在我国空间探测领域的应用,希望为核电子学技术在空间科学领域的进一步发展提供参考和见解。论文分析了几个空间科学任务中的核电子学设计方案,包括暗物质粒子探测卫星(Dark Matter Particle Explorer,DAMPE)、硬X射线调制望远镜(Hard X-ray Modulation Telescope,HXMT)、引力波暴高能电磁对应体全天监测器卫星(Gravitational Wave High-energy Electromagnetic Counterpart All-sky Monitor, GECAM)、天问一号(Tianwen-1)、先进天基太阳天文台(Advanced Space-based Solar Observatory, ASO-S)和爱因斯坦探针卫星(Einstein Probe,EP)等。在此基础上,本文进一步探讨了核电子学技术对于实现空间探测科学目标的重要性及其面临的挑战,包括创新性、空间环境适应能力等方面,并对未来的发展方向进行了展望。核电子学是核与粒子探测的核心技术,在空间科学任务中,核电子学系统除必须满足对探测器信号进行精密读出等所需要达到的电性能参数方面的要求,还要确保在太空特殊环境中的长期可靠性。此外,随着科学目标的拓展和提升,空间探测任务对核电子学的数据处理和传输能力也提出了更高的要求。同时,受益于新材料、先进工艺和人工智能等技术的发展,未来的核电子学系统有望更紧凑、可靠和智能化。核电子学的持续发展有望为实现更高水平的空间科学探测提供强有力的支持,推动对宇宙空间的更深度探索。

基于AlGaN/GaN场效应晶体管的太赫兹焦平面成像传感器

太赫兹波成像技术在人体安检、医学成像、无损检测等领域具有广泛的应用前景。文中面向高速、高灵敏度和便携式太赫兹成像应用需求,设计实现了一种基于AlGaN/GaN高电子迁移率晶体管自混频检测机制的太赫兹焦平面成像传感器。该焦平面成像传感器由探测器阵列芯片和CMOS读出电路通过倒装互连实现,阵列规模达到32×32。探测器阵列中具有对管差分功能的像元设计通过提高探测器的电压响应度和抑制共模电压噪声,提高了焦平面成像的灵敏度。焦平面成像传感器的输出模拟信号通过片外的模数转换(ADC)芯片转化为数字信号,由现场可编程门阵列(FPGA)采集后通过Camera Link图像数据与通信接口发送到计算机。利用该焦平面成像传感器,演示实现了太赫兹光斑、太赫兹干涉环和太赫兹光照下的旋转塑料叶片的视频成像,帧频达到30 Hz。