Design and prototyping of the readout electronics for the transition radiation detector in the high energy cosmic radiation detection facility

The high energy cosmic-radiation detection(HERD)facility is planned to launch in 2027 and scheduled to be installed on the China Space Station.It serves as a dark matter particle detector,a cosmic ray instrument,and an observatory for high-energy gamma rays.A transition radiation detector placed on one of its lateral sides serves dual purpose,(ⅰ)calibrating HERD's electromagnetic calorimeter in the TeV energy range,and(ⅱ)serving as an independent detector for high-energy gamma rays.In this paper,the prototype readout electronics design of the transition radiation detector is demonstrated,which aims to accurately measure the charge of the anodes using the SAMPA application specific integrated circuit chip.The electronic performance of the prototype system is evaluated in terms of noise,linearity,and resolution.Through the presented design,each electronic channel can achieve a dynamic range of 0–100 fC,the RMS noise level not exceeding 0.15 fC,and the integral nonlinearity was<0.2%.To further verify the readout electronic performance,a joint test with the detector was carried out,and the results show that the prototype system can satisfy the requirements of the detector's scientific goals.

Development of front-end readout electronics for silicon strip detectors

Front-end readout electronics have been developed for silicon strip detectors at our institute. In this system an Application Specific Integrated Circuit （ASIC） ATHED is used to realize multi-channel energy and time measurements. The slow control of ASIC chips is achieved by parallel port and the timing control signals of ASIC chips are implemented with the CPLD. The data acquisition is carried out with a PXI-DAQ card. The software has a user-friendly GUI developed with LabWindows/CVI in the Windows XP operating system. The test results show that the energy resolution is about 1.14% for alpha at 5.48 MeV and the maximum channel crosstalk of the system is 4.60%. The performance of the system is very reliable and is suitable for nuclear physics experiments.

Design and development of multi-channel front end electronics based on dual-polarity charge-to-digital converter for SiPM detector applications

With the development of silicon photomultiplier(SiPM)technology,front-end electronics for SiPM signal processing have been highly sought after in various fields.A compact 64-channel front-end electronics(FEE)system achieved by fieldprogrammable gate array-based charge-to-digital converter(FPGA-QDC)technology was built and developed.The FEE consists of an analog board and FPGA board.The analog board incorporates commercial amplifiers,resistors,and capacitors.The FPGA board is composed of a low-cost FPGA.The electronics performance of the FEE was evaluated in terms of noise,linearity,and uniformity.A positron emission tomography(PET)detector with three different readout configurations was designed to validate the readout capability of the FEE for SiPM-based detectors.The PET detector was made of a 15×15 lutetium–yttrium oxyorthosilicate(LYSO)crystal array directly coupled with a SiPM array detector.The experimental results show that FEE can process dual-polarity charge signals from the SiPM detectors.In addition,it shows a good energy resolution for 511-keV gamma photons under the dual-end readout for the LYSO crystal array irradiated by a Na-22 source.Overall,the FEE based on FPGA-QDC shows promise for application in SiPM-based radiation detectors.

Readout electronics for a high-resolution soft X-ray spectrometer based on silicon drift detector

The readout electronics for a prototype soft X-ray spectrometer based on silicon drift detector(SDD),for precisely measuring the energy and arrival time of X-ray photons is presented in this paper.The system mainly consists of two parts,i.e.,an analog electronics section(including a pre-amplifier,a signal shaper and filter,a constant fraction timing circuit,and a peak hold circuit)and a digital electronics section(including an ADC and a TDC).Test results with X-ray sources show that an energy dynamic range of 1-10 keV with an integral nonlinearity of less than 0.1%can be achieved,and the energy resolution is better than 160 eV @ 5.9 keV FWHM.Using a waveform generator,test results also indicate that time resolution of the electronics system is about 3.7 ns,which is much less than the transit time spread of SDD(<100 ns)and satisfies the requirements of future applications.

Readout electronics of a prototype time-of-flight ion composition analyzer for space plasma

Readout electronics is developed for a prototype time-of-flight(TOF) ion composition spectrometer for in situ measurement of the mass/charge distributions of major ion species from 200 to 100 ke V/e in space plasma.By utilizing a constant fraction discriminator(CFD) and time-to-digital converter(TDC), challenging dynamic range measurements were performed with high time resolution and event rates. CFD was employed to discriminate the TOF signals from the micro-channel plate and channel electron multipliers. TDC based on the combination of counter and OR-gate delay chain was designed in a highreliability flash field programmable gate array. Owing to the non-uniformity of the delay chain, a correction algorithm based on integral nonlinearity compensation was implemented to reduce the time uncertainty. The test results showed that the electronics achieved a low timingerror of < 200 ps in the input range from 35 to 500 m V for the CFD, and a time resolution of ～550 ps with time uncertainty < 180 ps after correction and a time range of6.4 ls for the TDC. The TOF spectrum from an electron beam experiment of the impacting N_2 gas further indicated the good performance of this readout electronic.

Design and evaluation of prototype readout electronics for nuclide detector in Very Large Area Space Telescope

China plans to develop the next generation dark matter particle explorer satellite,referred to as the Very Large Area Space Telescope(VLAST).As an essential step in this process,the prototype design of detectors and electronics for the VLAST is currently underway.The nuclide detector is a core detector in the VLAST.It mainly measures nuclides’charges and distinguishes high-energy gamma rays and electrons.This paper will discuss the prototype readout electronics for the VLAST’s nuclide detector,which accurately measures the charge signal of the photomultiplier tubes using the VATA160 applicationspecific integrated circuit chip;furthermore,we consider a series of critical problems,including radiation-hardening and environment monitoring.The test results show that the system exhibits stable operation,good performance,and good technical indicators.Furthermore,each electronic channel achieves a dynamic range of 0-12.5 pC,the random noise level exceeds 1.6 fC,and the integral nonlinearity exceeds 0.35%.

Prototype of the readout electronics for the RICH PID detector in the STCF

The ring imaging Cherenkov(RICH) detector for particle identification(PID) is being evaluated for the future super tau-charm facility(STCF) complex. In this work, the prototype readout electronics for the RICH PID detector is designed. The prototype RICH PID detector is based on a thick gas electron multiplier combined with a micromegas detector for Cherenkov light detection. Considering that there will be a large number(~ 690,000) of detector channels in future RICH detector, the readout electronics faces many challenges to precisely measuring time and charge information, such as reducing the noise,increasing density, and improving precision. The requirements of the readout electronics are explored, the downselection of the ASICs is made and thus a prototype readout electronics is designed and implemented. Tests are also conducted to evaluate the performance of the prototype readout electronics, and the results indicate that the time resolution is better than ~ 1 ns(RMS) when the input charge is greater than ~ 12 fC based on the APV25chip, while the time resolution is better than ~ 1 ns(RMS) at an input charge of over ~ 48 fC based on the AGET and STCF ASIC chips, and the equivalent noise charge is better than ~ 0.5 fC(RMS) @ 20 pF based on the three ASICs. The test results indicate that the prototype readout electronics design meets the requirement of the future RICH PID detector and thus provides a reference for future engineering.

Readout electronics of a prototype spectrometer for measuring low-energy ions in solar wind plasma

Readout electronics is developed for a prototype spectrometer for in situ measurement of low-energy ions of30 e V/e–20 ke V/e in the solar wind plasma.A low-noise preamplifier/discriminator(A111F) is employed for each channel to process the signal from micro-channel plate(MCP) detectors.A high-voltage(HV) supply solution based on a HV module and a HV optocoupler is adopted to generate a fast sweeping HV and a fixed HV.Due to limitation of telemetry bandwidth in space communication,an algorithm is implemented in an FPGA(field programmable gate array) to compress the raw data.Test results show that the electronics achieves a 1 MHz event rate and a large input dynamic range of 95 p C.A slew rate of 0.8 V/ls and an integral nonlinearity of 0.7-LSB for the sweeping HV,and a precision of less than 0.8 % for the fixed HV are obtained.A vacuum beam test shows an energy resolution of 12 ± 0.7 % full width at half maximum(FWHM) is achieved,and noise counts are less than10/sec,indicating that the performance meets the physical requirement.

Low-power SiPM readout BETA ASIC for space applications

The BETA application-specific integrated circuit(ASIC)is a fully programmable chip designed to amplify,shape and digitize the signal of up to 64 Silicon photomultiplier(SiPM)channels,with a power consumption of approximately~1 mW/channel.Owing to its dual-path gain,the BETA chip is capable of resolving single photoelectrons(phes)with a signal-to-noise ratio(SNR)>5 while simultaneously achieving a dynamic range of~4000 phes.Thus,BETA can provide a cost-effective solution for the readout of SiPMs in space missions and other applications with a maximum rate below 10 kHz.In this study,we describe the key characteristics of the BETA ASIC and present an evaluation of the performance of its 16-channel version,which is implemented using 130 nm technology.The ASIC also contains two discriminators that can provide trigger signals with a time jitter down to 400 ps FWHM for 10 phes.The linearity error of the charge gain measurement was less than 2%for a dynamic range as large as 15 bits.

Studies of an event-building algorithm of the readout system for the twin TPCs in HFRS

The High-energy Fragment Separator(HFRS),which is currently under construction,is a leading international radioactive beam device.Multiple sets of position-sensitive twin time projection chamber(TPC)detectors are distributed on HFRS for particle identification and beam monitoring.The twin TPCs'readout electronics system operates in a trigger-less mode due to its high counting rate,leading to a challenge of handling large amounts of data.To address this problem,we introduced an event-building algorithm.This algorithm employs a hierarchical processing strategy to compress data during transmission and aggregation.In addition,it reconstructs twin TPCs'events online and stores only the reconstructed particle information,which significantly reduces the burden on data transmission and storage resources.Simulation studies demonstrated that the algorithm accurately matches twin TPCs'events and reduces more than 98%of the data volume at a counting rate of 500 kHz/channel.

The front-end electronics design of dose monitors for beam delivery system of Shanghai Advanced Proton Therapy Facility

A front-end electronics of dose monitor has been developed for measuring irradiation dose to the patient in Shanghai Advanced Proton Therapy Facility.The parallel plate ionization chamber is used for the dose monitoring.Unlike the traditional method of recycling capacitor integration and voltage-to-frequency conversion,this dose monitor electronics uses the trans-impedance amplifier and analog-to-digital conversion method.It performs satisfactorily,with the integral nonlinearity of less than ±0.04 nA in the range of-400 to 50 nA and the resolution of about±0.6 nA.

Readout electronics for CSR-ETF silicon strip array detector system

A readout electronics has been developed for the silicon strip array detector system of HIRFL-CSR-ETF.It consists of 48 front end electronics(FEE)boards,12 PXI-DAQ boards and one trigger board.It can implement energy and time measurements of 4608 channels.Each FEE board is based on 6 ASICs(ATHED),which implements energy and time measurements of 96 channels.The PXI-DAQ board meets requirements of high-speed counting and amount of readout channels and can process signals of 4 FEEs.The trigger board is developed to select the valid events.The energy linearity of the readout electronics is better than 0.3%in the dynamic range of 0.1-0.7V.In the test with a standard triple alpha source,the energy resolution was 1.8%at 5.48 MeV.This readout electronics enables the silicon strip array system to identify particles of A<14.

Design of a high-dynamic-range prototype readout system for VLAST calorimeter

In the future, the Very Large Area gamma-ray Space Telescope is expected to observe high-energy electrons and gamma rays in the MeV to TeV range with unprecedented acceptance. As part of the detector suite, a high-energy imaging calorimeter(HEIC) is currently being developed as a homogeneous calorimeter that utilizes long bismuth germanate(BGO) scintillation crystals as both absorbers and detectors. To accurately measure the energy deposition in the BGO bar of HEIC, a highdynamic-range readout method using a silicon photomultiplier(SiPM) and multiphotodiode(PD) with different active areas has been proposed. A prototype readout system that adopts multichannel charge measurement ASICs was also developed to read out the combined system of SiPMs and PDs. Preliminary tests confirmed the feasibility of the readout scheme, which is expected to have a dynamic range close to 10~6.

Design of a Low-Noise Front-End Readout CSP-Shaper System for CZT Detectors

This paper describes a low-noise front-end readout circuit for CZT detectors based on TSMC 0.35 um mixed-single CMOS technology;mainly analyzes the noise model of the detector-preamplifier and presents the low-noise circuit schematic of charge sensitive preamplifier and shaper. Considering the parasitical influences, the circuit and layout-design are optimized to reduce noise. The preliminary simulation results show that, the equivalent noise charge (ENC) is 74 e﹣ (rms), noise slope is 9 e﹣/pF, power consumption is 2 mW, and non-linearity

Development of VME system in RPC electronics for reactor neutrino experiment at Daya Bay Nuclear Power Plant

VME system of the Resistive Plate Chamber (RPC) electronics for the Daya Bay Reactor Neutrino Experiment is described in this paper. A 9U VME RPC trigger module (RTM) is designed to process coincidence signals coming from front end cards (FECs), to generate local triggers and send them to FECs to select the hit data from RPC detector, to report trigger information to a master trigger system and receive cross triggers from the master trigger system. Another 9U VME readout module is designed to collect data from all FECs, to send out configurations to FECs, and to transmit collected hit data to the data acquisition system via VME bus. Test results prove that the VME system is capable of treating a maximum data rate (2.2 MB·s-1 ), without data loss.

Design of a Novel Front-End Readout ASIC for PET Imaging System

The architecture of a multi-channel front-end system is important for realizing a high-resolution PET system. We propose a novel front-end readout electronic system with TDC to deal with time information for PET system which can easily design the timing control. Each channel consists of a charge preamplifier, slow/fast shaper, discriminator and an analog memory. There are an ADC and a TDC to process the energy information and time information for each channel at the same time. In this paper, the whole system signals flow is all simulated by MATLAB. The simulation results show that the proposed system can process slender current from the detector and achieve the energy and time information. The proposed architecture can be applied to high-resolution PET imaging systems with multi-channel ASICs.

Front-end Control Mechanism of Electronic Records

In the digital era,how to ensure the authenticity and integrity of elec-tronic records has become an open challenging issue.Front-end control is an important concept as well as a basic principle in electronic record management.Under the instruction of front-end control,many original management links in the record-management stage are required to move forward,and the managers enter the formation stage of the electronic records to ensure the originality.How-ever,the front-end control technique primarily focuses on transaction manage-ment,and it lacks the strategy of providing the control of electronic records.In this paper,a novel electronic record front-end control mechanism is proposed by adopting proxy re-encryption and requiring archivists to participate in the man-agement of electronic records before the record is created to solve the problem.Specifically,when an electronic record is generated,the proposed mechanism interacts with the producer of the electronic record to generate a corresponding encryption key.Moreover,electronic records are encrypted by the key to protect their confidentiality,which can prevent the leakage of electronic record informa-tion.In addition,when transferring the electronic record,archivists use proxy re-encryption technology to convert electronic records,allowing management by an archivist,ensuring their originality and authenticity.

Design of a Low-Noise Front-End Readout Circuit for CdZnTe Detectors

In this paper, the design of a novel low-noise front-end readout circuit for Cadmium zinc telluride (CdZnTe) X-ray and γ-ray detectors is described. The front-end readout circuits include the charge sensitive amplifier (CSA) and the CR-RC shaper is implemented in TSMC 0.35 μm mixed-signal CMOS technology. The die size of the prototype chip is 4.9 mm × 2.2 mm. The simulation results show that, the noise performance is 46 electrons + 10 electrons/pF, and power consumption is 1.65 mW per channel.

Low-temperature metal–oxide thin-film transistor technologies for implementing flexible electronic circuits and systems

Here we review two 300℃metal–oxide(MO)thin-film transistor(TFT)technologies for the implementation of flexible electronic circuits and systems.Fluorination-enhanced TFTs for suppressing the variation and shift of turn-on voltage(VON),and dual-gate TFTs for acquiring sensor signals and modulating VON have been deployed to improve the robustness and performance of the systems in which they are deployed.Digital circuit building blocks based on fluorinated TFTs have been designed,fabricated,and characterized,which demonstrate the utility of the proposed low-temperature TFT technologies for implementing flexible electronic systems.The construction and characterization of an analog front-end system for the acquisition of bio-potential signals and an active-matrix sensor array for the acquisition of tactile images have been reported recently.

基于运算放大器的超导纳米线单光子探测器低温直流耦合读出电路

超导纳米线单光子探测器(SNSPD)具有高计数率、高探测效率和低暗计数等优点,在光量子通信、光量子计算、激光测距与成像等领域发挥着重要作用.SNSPD的最大计数率(探测速度)会受前级读出电路的影响,为了提升最大计数率,通常需要使用一个宽带宽的低温直流耦合读出电路.本文报道了基于商用高速运算放大芯片OPA855搭建的SNSPD低温直流耦合放大读出电路,系统表征了该电路从室温300 K到低温4.2 K下的性能参数.通过提升OPA855的工作电压,解决了电路在低温下带宽损失的问题.进一步,将OPA855放大电路安装在40 K温区,使用其实现了SNSPD探测性能的实验评估.相对于常规室温交流耦合电路,SNSPD的最大计数率约提升了1.3倍.本研究可为OPA855芯片在高速SNSPD等低温领域提供相关参考信息.