Based on 3 D-TCAD simulations, single-event transient(SET) effects and charge collection mechanisms in fully depleted silicon-on-insulator(FDSOI) transistors are investigated. This work presents a comparison between28...Based on 3 D-TCAD simulations, single-event transient(SET) effects and charge collection mechanisms in fully depleted silicon-on-insulator(FDSOI) transistors are investigated. This work presents a comparison between28-nm technology and 0.2-lm technology to analyze the impact of strike location on SET sensitivity in FDSOI devices. Simulation results show that the most SET-sensitive region in FDSOI transistors is the drain region near the gate. An in-depth analysis shows that the bipolar amplification effect in FDSOI devices is dependent on the strike locations. In addition, when the drain contact is moved toward the drain direction, the most sensitive region drifts toward the drain and collects more charge. This provides theoretical guidance for SET hardening.展开更多
A temperature-dependent model for threshold voltage and potential distribution of fully depleted silicon-on- insulator metal-oxide-semiconductor field-effect transistors is developed. The two-dimensional potential dis...A temperature-dependent model for threshold voltage and potential distribution of fully depleted silicon-on- insulator metal-oxide-semiconductor field-effect transistors is developed. The two-dimensional potential distribution function in the silicon thin film based on an approximate parabolic function has been applied to solve the two-dimensional Poisson＇s equation with suitable boundary conditions. The minimum of the surface potential is used to deduce the threshold voltage model. The model reveals the variations of potential distribution and threshold voltage with temperature, taking into account short-channel effects. Furthermore, the model is verified by the SILVACO ATLAS simulation. The calculations and the simulation agree well.展开更多
The n-type ultrathin fully depleted silicon-on-insulator(FDSOI) metal-oxide-semiconductor field-effect transistors(MOSFETs),with a Hf_(0.5)Zr_(0.5)O_(2) high dielectric permittivity(high-k) dielectric as gate insulato...The n-type ultrathin fully depleted silicon-on-insulator(FDSOI) metal-oxide-semiconductor field-effect transistors(MOSFETs),with a Hf_(0.5)Zr_(0.5)O_(2) high dielectric permittivity(high-k) dielectric as gate insulator,were fabricated.The total ionizing dose effects were investigated,and an X-ray radiation dose up to 1500 krad(Si) was applied for both long-and short-channel devices.The short-channel devices(0.025-0.100 μm) exhibited less irradiation sensitivity compared with the long-channel devices(0.35-16 μm),leading to a 71% reduction in the irradiation-induced drain current growth and a 26% decrease in the shift of the threshold voltage.It was experimentally demonstrated that the OFF mode is the worst case among the three working conditions(OFF,ON and A110) for short-channel devices.Also,the determined effective electron mobility was enhanced by 38% after X-ray irradiation,attributed to the different compensations for charges triggered by radiation between the highk dielectric and buried oxide.By extracting the carrier mobility,gate length modulation,and source/drain(S/D)parasitic resistance,the degradation mechanism on X-ray irradiation was revealed.Finally,the split capacitance-voltage measurements were used to validate the analysis.展开更多
A new 2D analytical drain current model is presented for symmetric double-gate fully depleted nanoscale SOI MOSFETs.Investigation of device parameters like transconductance for double-gate fully depleted nanoscale SOI...A new 2D analytical drain current model is presented for symmetric double-gate fully depleted nanoscale SOI MOSFETs.Investigation of device parameters like transconductance for double-gate fully depleted nanoscale SOI MOSFETs is also carried out.Finally this work is concluded by modeling the cut-off frequency, which is one of the main figures of merit for analog/RF performance for double-gate fully depleted nanoscale SOI MOSFETs.The results of the modeling are compared with those obtained by a 2D ATLAS device simulator to verify the accuracy of the proposed model.展开更多
The importance ofsubstrate doping engineering for extremely thin SOI MOSFETs with ultra-thin buried oxide （ES-UB-MOSFETs） is demonstrated by simulation. A new substrate/backgate doping engineering, lateral non-unifo...The importance ofsubstrate doping engineering for extremely thin SOI MOSFETs with ultra-thin buried oxide （ES-UB-MOSFETs） is demonstrated by simulation. A new substrate/backgate doping engineering, lateral non-uniform dopant distributions （LNDD） is investigated in ES-UB-MOSFETs. The effects of LNDD on device performance, Vt-roll-off, channel mobility and random dopant fluctuation （RDF） are studied and optimized. Fixing the long channel threshold voltage （Vt） at 0.3 V, ES-UB-MOSFETs with lateral uniform doping in the substrate and forward back bias can scale only to 35 nm, meanwhile LNDD enables ES-UB-MOSFETs to scale to a 20 nm gate length, which is 43% smaller. The LNDD degradation is 10% of the carrier mobility both for nMOS and pMOS, but it is canceled out by a good short channel effect controlled by the LNDD. Fixing Vt at 0.3 V, in long channel devices, due to more channel doping concentration for the LNDD technique, the RDF in LNDD controlled ES-UB-MOSFETs is worse than in back-bias controlled ES-UB-MOSFETs, but in the short channel, the RDF for LNDD controlled ES-UB-MOSFET is better due to its self-adaption of substrate doping engineering by using a fixed thickness inner-spacer. A novel process flow to form LNDD is proposed and simulated.展开更多
基金supported by the National Natural Science Foundation of China(Nos.61434007 and 61376109)
文摘Based on 3 D-TCAD simulations, single-event transient(SET) effects and charge collection mechanisms in fully depleted silicon-on-insulator(FDSOI) transistors are investigated. This work presents a comparison between28-nm technology and 0.2-lm technology to analyze the impact of strike location on SET sensitivity in FDSOI devices. Simulation results show that the most SET-sensitive region in FDSOI transistors is the drain region near the gate. An in-depth analysis shows that the bipolar amplification effect in FDSOI devices is dependent on the strike locations. In addition, when the drain contact is moved toward the drain direction, the most sensitive region drifts toward the drain and collects more charge. This provides theoretical guidance for SET hardening.
文摘A temperature-dependent model for threshold voltage and potential distribution of fully depleted silicon-on- insulator metal-oxide-semiconductor field-effect transistors is developed. The two-dimensional potential distribution function in the silicon thin film based on an approximate parabolic function has been applied to solve the two-dimensional Poisson＇s equation with suitable boundary conditions. The minimum of the surface potential is used to deduce the threshold voltage model. The model reveals the variations of potential distribution and threshold voltage with temperature, taking into account short-channel effects. Furthermore, the model is verified by the SILVACO ATLAS simulation. The calculations and the simulation agree well.
基金financially supported by the National Natural Science Foundation of China (Nos.61874135,61904194 and 11905287)the National Major Project of Science and Technology of China (No.2017ZX02315001)+1 种基金the Youth Innovation Promotion Association,CAS (No.Y9YQ01R004)the Opening Project of Key Laboratory of Microelectronic Devices & Integrated Technology,Institute of Microelectronics,CAS (No.Y9YS05X002)。
文摘The n-type ultrathin fully depleted silicon-on-insulator(FDSOI) metal-oxide-semiconductor field-effect transistors(MOSFETs),with a Hf_(0.5)Zr_(0.5)O_(2) high dielectric permittivity(high-k) dielectric as gate insulator,were fabricated.The total ionizing dose effects were investigated,and an X-ray radiation dose up to 1500 krad(Si) was applied for both long-and short-channel devices.The short-channel devices(0.025-0.100 μm) exhibited less irradiation sensitivity compared with the long-channel devices(0.35-16 μm),leading to a 71% reduction in the irradiation-induced drain current growth and a 26% decrease in the shift of the threshold voltage.It was experimentally demonstrated that the OFF mode is the worst case among the three working conditions(OFF,ON and A110) for short-channel devices.Also,the determined effective electron mobility was enhanced by 38% after X-ray irradiation,attributed to the different compensations for charges triggered by radiation between the highk dielectric and buried oxide.By extracting the carrier mobility,gate length modulation,and source/drain(S/D)parasitic resistance,the degradation mechanism on X-ray irradiation was revealed.Finally,the split capacitance-voltage measurements were used to validate the analysis.
文摘A new 2D analytical drain current model is presented for symmetric double-gate fully depleted nanoscale SOI MOSFETs.Investigation of device parameters like transconductance for double-gate fully depleted nanoscale SOI MOSFETs is also carried out.Finally this work is concluded by modeling the cut-off frequency, which is one of the main figures of merit for analog/RF performance for double-gate fully depleted nanoscale SOI MOSFETs.The results of the modeling are compared with those obtained by a 2D ATLAS device simulator to verify the accuracy of the proposed model.
基金supported by the Opening Project of Key Laboratory of Microelectronics Devices & Integrated Technology,Institute of Microelectronics the China National S & T Major Project 02
文摘The importance ofsubstrate doping engineering for extremely thin SOI MOSFETs with ultra-thin buried oxide （ES-UB-MOSFETs） is demonstrated by simulation. A new substrate/backgate doping engineering, lateral non-uniform dopant distributions （LNDD） is investigated in ES-UB-MOSFETs. The effects of LNDD on device performance, Vt-roll-off, channel mobility and random dopant fluctuation （RDF） are studied and optimized. Fixing the long channel threshold voltage （Vt） at 0.3 V, ES-UB-MOSFETs with lateral uniform doping in the substrate and forward back bias can scale only to 35 nm, meanwhile LNDD enables ES-UB-MOSFETs to scale to a 20 nm gate length, which is 43% smaller. The LNDD degradation is 10% of the carrier mobility both for nMOS and pMOS, but it is canceled out by a good short channel effect controlled by the LNDD. Fixing Vt at 0.3 V, in long channel devices, due to more channel doping concentration for the LNDD technique, the RDF in LNDD controlled ES-UB-MOSFETs is worse than in back-bias controlled ES-UB-MOSFETs, but in the short channel, the RDF for LNDD controlled ES-UB-MOSFET is better due to its self-adaption of substrate doping engineering by using a fixed thickness inner-spacer. A novel process flow to form LNDD is proposed and simulated.
