It is still challenging to fully integrate computing in memory chip as edge learning devices.In recent work published on Science,a fully-integrated chip based on neuromorphic memristors was developed for edge learning...It is still challenging to fully integrate computing in memory chip as edge learning devices.In recent work published on Science,a fully-integrated chip based on neuromorphic memristors was developed for edge learning as artificial neural networks with functionality of synapses,dendrites,and somas.A crossbar-array memristor chip facilitated edge learning including hardware realization,learning algorithm,and cycle-parallel sign-and threshold-based learning(STELLAR)scheme.The motion control and demonstration platforms were executed to improve the edge learning ability for adapting to new scenarios.展开更多
A UHF RF identification system based on the 0.18μm CMOS process has been developed for short range and harsh size requirement applications, which is composed of a fully integrated tag and a special reader. The whole ...A UHF RF identification system based on the 0.18μm CMOS process has been developed for short range and harsh size requirement applications, which is composed of a fully integrated tag and a special reader. The whole tag chip with the antenna takes up an area of 0.36 mm^2, which is smaller than other reported tags with an on-chip antenna （OCA） using the standard CMOS process. A self-defined protocol is proposed to reduce the power consumption, and minimize the size of the tag. The specialized SOC reader system consists of the RF transceiver, digital baseband, MCU and host interface. Its power consumption is about 500 mW. Measurement results show that the system＇s reading range is 2 mm with 20 dBm reader output power. With an inductive antenna printed on a paper substrate around the OCA tag, the reading range can be extended from several centimeters to meters, depending on the shape and size of the inductive antenna.展开更多
A fully integrated 2n/2n＋1 dual-modulus divider in GHz frequency range is presented. The improved structure can make all separated logic gates embed into correlative D flip-flops completely. In this way, the complex ...A fully integrated 2n/2n＋1 dual-modulus divider in GHz frequency range is presented. The improved structure can make all separated logic gates embed into correlative D flip-flops completely. In this way, the complex logic functions can be performed with a minimum number of devices and with maximum speed, so that lower power consumption and faster speed are obtained. In addition, the low-voltage bandgap reference needed by the frequency divider is specifically designed to provide a 1.0 V output. According to the design demand, the circuit is fabricated in 0.18 μm standard CMOS process, and the measured results show that its operating frequency range is 1.1- 2.5 GHz. The dual-modulus divider dissipates 1.1 mA from a 1.8 V power supply. The temperature coefficient of the reference voltage circuit is 8.3 ppm/℃ when the temperature varies from -40 to ＋ 125 ℃. By comparison, the dual-modulus divide designed in this paper can possess better performance and flexibility.展开更多
基金funding support from the National Natural Science Foundation of China(52172205).
文摘It is still challenging to fully integrate computing in memory chip as edge learning devices.In recent work published on Science,a fully-integrated chip based on neuromorphic memristors was developed for edge learning as artificial neural networks with functionality of synapses,dendrites,and somas.A crossbar-array memristor chip facilitated edge learning including hardware realization,learning algorithm,and cycle-parallel sign-and threshold-based learning(STELLAR)scheme.The motion control and demonstration platforms were executed to improve the edge learning ability for adapting to new scenarios.
文摘A UHF RF identification system based on the 0.18μm CMOS process has been developed for short range and harsh size requirement applications, which is composed of a fully integrated tag and a special reader. The whole tag chip with the antenna takes up an area of 0.36 mm^2, which is smaller than other reported tags with an on-chip antenna （OCA） using the standard CMOS process. A self-defined protocol is proposed to reduce the power consumption, and minimize the size of the tag. The specialized SOC reader system consists of the RF transceiver, digital baseband, MCU and host interface. Its power consumption is about 500 mW. Measurement results show that the system＇s reading range is 2 mm with 20 dBm reader output power. With an inductive antenna printed on a paper substrate around the OCA tag, the reading range can be extended from several centimeters to meters, depending on the shape and size of the inductive antenna.
基金supported by the Open Program of National Short-wave Communication Engineering Technology Research Centre(No.HF2013002)
文摘A fully integrated 2n/2n＋1 dual-modulus divider in GHz frequency range is presented. The improved structure can make all separated logic gates embed into correlative D flip-flops completely. In this way, the complex logic functions can be performed with a minimum number of devices and with maximum speed, so that lower power consumption and faster speed are obtained. In addition, the low-voltage bandgap reference needed by the frequency divider is specifically designed to provide a 1.0 V output. According to the design demand, the circuit is fabricated in 0.18 μm standard CMOS process, and the measured results show that its operating frequency range is 1.1- 2.5 GHz. The dual-modulus divider dissipates 1.1 mA from a 1.8 V power supply. The temperature coefficient of the reference voltage circuit is 8.3 ppm/℃ when the temperature varies from -40 to ＋ 125 ℃. By comparison, the dual-modulus divide designed in this paper can possess better performance and flexibility.
