Collisions between a moving mass and an anti-collision device increase structural responses and threaten structural safety.An active mass damper(AMD)with stroke limitations is often used to avoid collisions.However,a ...Collisions between a moving mass and an anti-collision device increase structural responses and threaten structural safety.An active mass damper(AMD)with stroke limitations is often used to avoid collisions.However,a strokelimited AMD control system with a fixed limited area shortens the available AMD stroke and leads to significant control power.To solve this problem,the design approach with variable gain and limited area(VGLA)is proposed in this study.First,the boundary of variable-limited areas is calculated based on the real-time status of the moving mass.The variable gain(VG)expression at the variable limited area is deduced by considering the saturation of AMD stroke.Then,numerical simulations of a stroke-limited AMD control system with VGLA are conducted on a high-rise building structure.These numerical simulations show that the proposed approach has superior strokelimitation performance compared with a stroke-limited AMD control system with a fixed limited area.Finally,the proposed approach is validated through experiments on a four-story steel frame.展开更多
We established a photoacoustic imaging(PAI)system that can provide variable gain at different depths.The PAI system consists of a pulsed laser with an optical parametric oscillator working at a 728 nmwavelength and an...We established a photoacoustic imaging(PAI)system that can provide variable gain at different depths.The PAI system consists of a pulsed laser with an optical parametric oscillator working at a 728 nmwavelength and an imaging-acquisition-and-processing unit with an ultrasound transducer.Avoltage-controlled attenuator was used to realize variable gain at different depths when acquiring PAI signals.The proof-of-concept imaging results for variable gain at different depths were achieved using specic phantoms.Both resolution and optical contrast obtained through the results of variable gain for a targeted depth range are better than those of constant gain for all depths.To further testify the function,we imaged the sagittal section of the body of in vivo nude mice.In addition,we imaged an absorption sample embedded in a chicken breast tissue,reaching a maximum imaging depth of4.6 cm.The results obtained using the proposed method showed better resolution and contrast than when using 50 dB gain for all depths.The depth range resolution was1 mm,and the maximum imaging depth of our system reached4.6 cm.Furthermore,blood vessels can be revealed and targeted depth range can be selected in nude mice imaging.展开更多
This paper presents a novel approach for designing a reconfigurable variable gain amplifier(VGA) for the multi-mode multi-band receiver system RF front-end applications.The configuration,which is comprised of gain c...This paper presents a novel approach for designing a reconfigurable variable gain amplifier(VGA) for the multi-mode multi-band receiver system RF front-end applications.The configuration,which is comprised of gain circuits,control circuit,DC offset cancellation circuit and mode switch circuit is proposed to save die area and power consumption with the function of multi-mode and multi-band through reusing.The VGA is realized in 0.18μm CMOS technology with 1.8 V power supply voltage providing a gain tuning range from 5 to 87 dB when the control voltage varies from 0 to 1.8 V.The 3 dB bandwidth is about 80 MHz for all levels of control voltage(all gains).Also,the DC offset cancellation circuit can effectively suppress DC offset to a value of less than 40 mV at the output regardless of the input.The overall power consumption is less than 3 mA,and die area is 705×100μm^2.展开更多
This paper presents a variable gain low-noise amplifier(VG-LNA) for 5 GHz applications.The effect of the input parasitic capacitance on the inductively degenerated common source LNA's input impedance is analyzed in...This paper presents a variable gain low-noise amplifier(VG-LNA) for 5 GHz applications.The effect of the input parasitic capacitance on the inductively degenerated common source LNA's input impedance is analyzed in detail.A new ESD and LNA co-design method was proposed to achieve good performance.In addition,by using a simple feedback loop at the second stage of the LNA,continuous gain control is realized.The measurement results of the proposed VG-LNA exhibit 25 dB(-3.3 dB to 21.7 dB) variable gain range,2.8 dB noise figure at the maximum gain and 1 dBm IIP3 at the minimum gain,while the DC power consumption is 9.9 mW under a 1.8 V supply voltage.展开更多
A CMOS variable gain low noise amplifier (LNA) is presented for 4.24.8 GHz ultra-wideband appli- cation in accordance with Chinese standard. The design method for the wideband input matching is presented and the low...A CMOS variable gain low noise amplifier (LNA) is presented for 4.24.8 GHz ultra-wideband appli- cation in accordance with Chinese standard. The design method for the wideband input matching is presented and the low noise performance of the LNA is illustrated. A three-bit digital programmable gain control circuit is exploited to achieve variable gain. The design was implemented in 0.13μm RF CMOS process, and the die occupies an area of 0.9 mm2 with ESD pads. Totally the circuit draws 18 mA DC current from 1.2 V DC supply, the LNA exhibits minimum noise figure of 2.3 dB, S(1, 1) less than -9 dB and S(2, 2) less than -10 dB. The maximum and the minimum power gains are 28.5 dB and 16 dB respectively. The tuning step of the gain is about 4 dB with four steps in all. Also the input 1 dB compression point is -10 dBm and input third order intercept point (IIP3) is -2 dBm.展开更多
A compact and reconfigurable low noise amplifier(LNA)is proposed by combining an input transistor,composite transistors with Darlington configuration as the amplification and output transistor,T-type structure composi...A compact and reconfigurable low noise amplifier(LNA)is proposed by combining an input transistor,composite transistors with Darlington configuration as the amplification and output transistor,T-type structure composite resistors instead of a simplex structure resistor,a shunt inductor feedback realized by a tunable active inductor(AI),a shunt inductor peaking technique realized by another tunable AI.The division and collaboration among different resistances in the T-type structure composite resistor realize simultaneously input impedance matching,output impedance matching and good noise performance;the shunt feedback and peaking technique using two tunable AIs not only extend frequency bandwidth and improve gain flatness,but also make the gain and frequency band can be tuned simultaneously by the external bias of tunable AIs;the Darlington configuration of composite transistors provides high gain;furthermore,the adoption of the small size AIs instead of large size passive spiral inductor,and the use of composite resistors make the LNA have a small size.The LNA is fabricated and verified by GaAs/InGaP hetero-junction bipolar transistor(HBT)process.The results show that at the frequency of 7 GHz,the gain S_(21)is maximum and up to 19 dB;the S_(21)can be tuned from 17 dB to 19 dB by tuning external bias of tunable AIs,that is,the tunable amount of S_(21)is 2 dB,and similarly at 8 GHz;the tunable range of 3 dB bandwidth is 1 GHz.In addition,the gain S_(21)flatness is better than 0.4 dB under frequency from 3.1 GHz to 10.6 GHz;the size of the LNA only has 760μm×1260μm(including PADs).Therefore,the proposed strategies in the paper provide a new solution to the design of small size and reconfigurable ultra-wideband(UWB)LNA and can be used further to adjust the variations of gain and bandwidth of radio frequency integrated circuits(RFICs)due to package,parasitic and the variation of fabrication process and temperature.展开更多
A CMOS variable gain amplifier(VGA) that adopts a novel exponential gain approximation is presented.No additional exponential gain control circuit is required in the proposed VGA used in a direct conversion receiver...A CMOS variable gain amplifier(VGA) that adopts a novel exponential gain approximation is presented.No additional exponential gain control circuit is required in the proposed VGA used in a direct conversion receiver.A wide gain control voltage from 0.4 to 1.8 V and a high linearity performance are achieved.The three-stage VGA with automatic gain control(AGC) and DC offset cancellation(DCOC) is fabricated in a 0.18-μm CMOS technology and shows a linear gain range of more than 58-dB with a linearity error less than ±1 dB.The 3-dB bandwidth is over 8 MHz at all gain settings.The measured input-referred third intercept point(IIP3) of the proposed VGA varies from-18.1 to 13.5 dBm,and the measured noise figure varies from 27 to 65 dB at a frequency of 1 MHz.The dynamic range of the closed-loop AGC exceeds 56 dB,where the output signal-to-noise-and-distortion ratio(SNDR) reaches 20 dB.The whole circuit,occupying 0.3 mm^2 of chip area,dissipates less than 3.7 mA from a 1.8-V supply.展开更多
A differential automatic gain control (AGC) circuit is presented. The AGC architecture contains twostage variable gain amplifiers (VGAs) which are implemented with a Gilbert cell, a peak detector (PD), a low pas...A differential automatic gain control (AGC) circuit is presented. The AGC architecture contains twostage variable gain amplifiers (VGAs) which are implemented with a Gilbert cell, a peak detector (PD), a low pass filter, an operational amplifier, and two voltage to current (V-I) convertors. One stage VGA achieves 30 dB gain due to the use of active load. The AGC circuit is implemented in UMC 0.18-um single-poly six-metal CMOS process technology. Measurement results show that the final differential output swing of the 2nd stage VGA is about 0.9-Vpp; the total gain of the two VGAs can be varied linearly from -10 to 50 dB when the control voltage varies from 0.3 to 0.9 V. The final circuit (containing output buffers and a band-gap reference) consumes 37 mA from single 1.8 V voltage supply. For a 50 mV amplitude 60% modulation depth input AM signal it needs 100 us to stabilize the output. The frequency response of the circuit has almost a constant -3 dB bandwidth of 2.2 MHz. Its OIP3 result is at 19 dBm.展开更多
This paper proposes a new structure to lower the power consumption of a variable gain amplifier(VGA) and keep the linearity of the VGA unchanged.The structure is used in a high rate amplitude-shift keying(ASK) bas...This paper proposes a new structure to lower the power consumption of a variable gain amplifier(VGA) and keep the linearity of the VGA unchanged.The structure is used in a high rate amplitude-shift keying(ASK) based IF-stage.It includes an automatic gain control(AGC) loop and ASK demodulator.The AGC mainly consists of sixstage VGAs.The IF-stage is realized in 0.18μm CMOS technology.The measurement results show that the power consumption of the whole system is very low.The system consumes 730μA while operating at 1.8 V.The minimum ASK signal the system could detect is 0.7 mV(peak to peak amplitude).展开更多
A broadband programmable gain amplifier(PGA) with a small gain step and low gain error has been designed in 0.13 m CMOS technology. The PGA was implemented with open-loop architecture to provide wide bandwidth. A tw...A broadband programmable gain amplifier(PGA) with a small gain step and low gain error has been designed in 0.13 m CMOS technology. The PGA was implemented with open-loop architecture to provide wide bandwidth. A two-stage gain control method, which consists of a resistor ladder attenuator and an active fine gain control stage, provides the small gain step. A look-up table based gain control method is introduced in the fine gain control stage to lower the gain error.The proposedPGAshows a decibel-linear variable gainfrom4 to20 dB with a gain step of 0.1 dB and a gain error less than˙0.05 dB. The 3-dB bandwidth and maximum IIP3 are 3.8 GHz and 17 dBm, respectively.展开更多
A CMOS RF front-end for the long-term evolution(LTE) direct conversion receiver is presented.With a low noise transconductance amplifier(LNA),current commutating passive mixer and transimpedance operational amplif...A CMOS RF front-end for the long-term evolution(LTE) direct conversion receiver is presented.With a low noise transconductance amplifier(LNA),current commutating passive mixer and transimpedance operational amplifier(TIA),the RF front-end structure enables high-integration,high linearity and simple frequency planning for LTE multi-band applications.Large variable gain is achieved using current-steering transconductance stages.A current commutating passive mixer with 25%duty-cycle LO improves gain,noise and linearity.A direct coupled current-input filter(DCF) is employed to suppress the out-of-band interferer.Fabricated in a 0.13-μm CMOS process,the RF front-end achieves a 45 dB conversion voltage gain,2.7 dB NF,-7 dBm IIP3,and +60 dBm IIP2 with calibration from 2.3 to 2.7 GHz.The total RF front end with divider draws 40 mA from a single 1.2-V supply.展开更多
A 5 Gb/s adaptive equalizer with a new adaptation scheme is presented here by using 0.13μm CMOS process. The circuit consists of the combination of equalizer amplifier, limiter amplifier and adaptation loop. The adap...A 5 Gb/s adaptive equalizer with a new adaptation scheme is presented here by using 0.13μm CMOS process. The circuit consists of the combination of equalizer amplifier, limiter amplifier and adaptation loop. The adaptive algorithm exploits both the low frequency gain loop and the equalizer loop to minimize the inter-symbol interference (ISI) for a variety of cable characteristics. In addition, an offset cancellation loop is used to alleviate the offset influence of the signal path. The adaptive equalizer core occupies an area of 0.3567 mm2 and consumes a power consumption of 81.7 mW with 1.8 V power supply. Experiment results demonstrate that the equalizer could compensate for a designed cable loss with 0.23 UI peak-to-peak jitter.展开更多
A wide tuning range,low power CMOS automatic gain control(AGC) with a simple architecture is proposed. The proposed AGC is composed of a variable gain amplifier(VGA),a comparator and a charge pump,and the dB-linea...A wide tuning range,low power CMOS automatic gain control(AGC) with a simple architecture is proposed. The proposed AGC is composed of a variable gain amplifier(VGA),a comparator and a charge pump,and the dB-linear gain is controlled by the charge pump.The AGC was implemented in a 0.18μm CMOS technology.The dynamic range of the VGA is more than 55 dB,the bandwidth is 30 MHz,and the gain error is lower than±1.5 dB over the full temperature and gain ranges.It is designed for GPS application and is fed from a single 1.8 V power supply. The AGC power consumption is less than 5 mW,and the area of the AGC is 700×450μm^2.展开更多
A wideband receiver RP front-end for IR-UWB applications is implemented in 0.13μm CMOS technology. Thanks to the direct sub-sampling architecture,there is no mixing process.Both LNA and VGA work at RF frequencies.To ...A wideband receiver RP front-end for IR-UWB applications is implemented in 0.13μm CMOS technology. Thanks to the direct sub-sampling architecture,there is no mixing process.Both LNA and VGA work at RF frequencies.To optimize noise as well as linearity,a differential common-source LNA with capacitive cross- coupling is used,which only consumes current of 1.8 mA from a 1.2 V power supply.Following LNA,a two-stage current-steering VGA is adopted for gain tuning.To extend the overall bandwidth,a three-stage staggered peaking technique is used.Measurement results show that the proposed receiver front-end achieves a gain tuning range from 5 to 40 dB within 6-7 GHz,a minimum noise figure of 4.5 dB and a largest IIP_3 of-11 dBm.The core receiver (without test buffer) consumes 14 mW from a 1.2 V power supply and occupies 0.58 mm^2 area.展开更多
This paper presents a low power 2.4 GHz transceiver for ZigBee applications.This transceiver adopts low power system architecture with a low-IF receiver and a direct-conversion transmitter.The receiver consists of a n...This paper presents a low power 2.4 GHz transceiver for ZigBee applications.This transceiver adopts low power system architecture with a low-IF receiver and a direct-conversion transmitter.The receiver consists of a new low noise amplifier(LNA) with a noise cancellation function,a new inverter-based variable gain complex filter (VGCF) for image rejection,a passive quadrature mixer,and a decibel linear programmable gain amplifier(PGA). The transmitter adopts a quadrature mixer and a class-B mode variable gain power amplifier(PA) to reduce power consumption.This transceiver is implemented in 0.18μm CMOS technology.The receiver achieves—95 dBm of sensitivity,28 dBc of image rejection,and -8 dBm of third-order input intercept point(IIP3).The transmitter can deliver a maximum of+3 dBm output power with PA efficiency of 30%.The whole chip area is less than 4.32 mm^2. It only consumes 12.63 mW in receiving mode and 14.22 mW in transmitting mode,respectively.展开更多
A 14-bit,40-MHz analog front end(AFE) for CCD scanners is analyzed and designed.The proposed system incorporates a digitally controlled wideband variable gain amplifier(VGA) with nearly 42 dB gain range,a correlat...A 14-bit,40-MHz analog front end(AFE) for CCD scanners is analyzed and designed.The proposed system incorporates a digitally controlled wideband variable gain amplifier(VGA) with nearly 42 dB gain range,a correlated double sampler(CDS) with programmable gain functionality,a 14-bit analog-to-digital converter and a programmable timing core.To achieve the maximum dynamic range,the VGA proposed here can linearly amplify the input signal in a gain range from-1.08 to 41.06 dB in 6.02 dB step with a constant bandwidth.A novel CDS takes image information out of noise,and further amplifies the signal accurately in a gain range from 0 to 18 dB in0.035 dB step.A 14-bit ADC is adopted to quantify the analog signal with optimization in power and linearity.An internal timing core can provide flexible timing for CCD arrays,CDS and ADC.The proposed AFE was fabricated in SMIC 0.18 μm CMOS process.The whole circuit occupied an active area of 2.8×4.8 mm^2 and consumed360 mW.When the frequency of input signal is 6.069 MHz,and the sampling frequency is 40 MHz,the signal to noise and distortion(SNDR) is 70.3 dB,the effective number of bits is 11.39 bit.展开更多
基金This research was founded by the Funds for Creative Research Groups of National Natural Science Foundation of China(Grant No.51921006)the National Natural Science Foundations of China(Grant No.51978224)+2 种基金the National Major Scientific Research Instrument Development Program of China(Grant No.51827811)the National Natural Science Foundation of China,(Grant No.52008141)the Shenzhen Technology Innovation Program(Grant Nos.JCYJ20170811160003571,JCYJ20180508152238111 and JCYJ20200109112803851).
文摘Collisions between a moving mass and an anti-collision device increase structural responses and threaten structural safety.An active mass damper(AMD)with stroke limitations is often used to avoid collisions.However,a strokelimited AMD control system with a fixed limited area shortens the available AMD stroke and leads to significant control power.To solve this problem,the design approach with variable gain and limited area(VGLA)is proposed in this study.First,the boundary of variable-limited areas is calculated based on the real-time status of the moving mass.The variable gain(VG)expression at the variable limited area is deduced by considering the saturation of AMD stroke.Then,numerical simulations of a stroke-limited AMD control system with VGLA are conducted on a high-rise building structure.These numerical simulations show that the proposed approach has superior strokelimitation performance compared with a stroke-limited AMD control system with a fixed limited area.Finally,the proposed approach is validated through experiments on a four-story steel frame.
基金the financial support fromNational Natural Science Foundation of China(NSFC)(61675113,61527808,81401539,and 31271056)Science and Technology Research Program of Shenzhen City(JSGG20150331151536448,JCYJ20160428182247170,and JCYJ20170412170255060)+1 种基金Shenzhen basic research layout project(JCYJ20160324163759208)the projects in Shenzhen Medical Engineering Laboratory For Human Auditory-equilibrium Function。
文摘We established a photoacoustic imaging(PAI)system that can provide variable gain at different depths.The PAI system consists of a pulsed laser with an optical parametric oscillator working at a 728 nmwavelength and an imaging-acquisition-and-processing unit with an ultrasound transducer.Avoltage-controlled attenuator was used to realize variable gain at different depths when acquiring PAI signals.The proof-of-concept imaging results for variable gain at different depths were achieved using specic phantoms.Both resolution and optical contrast obtained through the results of variable gain for a targeted depth range are better than those of constant gain for all depths.To further testify the function,we imaged the sagittal section of the body of in vivo nude mice.In addition,we imaged an absorption sample embedded in a chicken breast tissue,reaching a maximum imaging depth of4.6 cm.The results obtained using the proposed method showed better resolution and contrast than when using 50 dB gain for all depths.The depth range resolution was1 mm,and the maximum imaging depth of our system reached4.6 cm.Furthermore,blood vessels can be revealed and targeted depth range can be selected in nude mice imaging.
基金Project supported by the Core Electronic Devices,High-End General Chips and Basic Software Produces Major Projects,China(No. 2009ZX01031-002-008).
文摘This paper presents a novel approach for designing a reconfigurable variable gain amplifier(VGA) for the multi-mode multi-band receiver system RF front-end applications.The configuration,which is comprised of gain circuits,control circuit,DC offset cancellation circuit and mode switch circuit is proposed to save die area and power consumption with the function of multi-mode and multi-band through reusing.The VGA is realized in 0.18μm CMOS technology with 1.8 V power supply voltage providing a gain tuning range from 5 to 87 dB when the control voltage varies from 0 to 1.8 V.The 3 dB bandwidth is about 80 MHz for all levels of control voltage(all gains).Also,the DC offset cancellation circuit can effectively suppress DC offset to a value of less than 40 mV at the output regardless of the input.The overall power consumption is less than 3 mA,and die area is 705×100μm^2.
基金supported by the SEU-Winbond United Research Center and the National High Technology Research and Development Program of China(No.2007AA01Z2A7).
文摘This paper presents a variable gain low-noise amplifier(VG-LNA) for 5 GHz applications.The effect of the input parasitic capacitance on the inductively degenerated common source LNA's input impedance is analyzed in detail.A new ESD and LNA co-design method was proposed to achieve good performance.In addition,by using a simple feedback loop at the second stage of the LNA,continuous gain control is realized.The measurement results of the proposed VG-LNA exhibit 25 dB(-3.3 dB to 21.7 dB) variable gain range,2.8 dB noise figure at the maximum gain and 1 dBm IIP3 at the minimum gain,while the DC power consumption is 9.9 mW under a 1.8 V supply voltage.
基金Project supported by the National High Technology Research and Development Program of China(No.2007AA01Z2B1)the China National Science and Technology Major Special Program(No.2009ZX03006-008)+1 种基金the Shanghai ICC Foundation Program (No.10706200201)the Shanghai Informatization Fund Program
文摘A CMOS variable gain low noise amplifier (LNA) is presented for 4.24.8 GHz ultra-wideband appli- cation in accordance with Chinese standard. The design method for the wideband input matching is presented and the low noise performance of the LNA is illustrated. A three-bit digital programmable gain control circuit is exploited to achieve variable gain. The design was implemented in 0.13μm RF CMOS process, and the die occupies an area of 0.9 mm2 with ESD pads. Totally the circuit draws 18 mA DC current from 1.2 V DC supply, the LNA exhibits minimum noise figure of 2.3 dB, S(1, 1) less than -9 dB and S(2, 2) less than -10 dB. The maximum and the minimum power gains are 28.5 dB and 16 dB respectively. The tuning step of the gain is about 4 dB with four steps in all. Also the input 1 dB compression point is -10 dBm and input third order intercept point (IIP3) is -2 dBm.
基金Supported by the National Natural Science Foundation of China(No.61774012,61574010)。
文摘A compact and reconfigurable low noise amplifier(LNA)is proposed by combining an input transistor,composite transistors with Darlington configuration as the amplification and output transistor,T-type structure composite resistors instead of a simplex structure resistor,a shunt inductor feedback realized by a tunable active inductor(AI),a shunt inductor peaking technique realized by another tunable AI.The division and collaboration among different resistances in the T-type structure composite resistor realize simultaneously input impedance matching,output impedance matching and good noise performance;the shunt feedback and peaking technique using two tunable AIs not only extend frequency bandwidth and improve gain flatness,but also make the gain and frequency band can be tuned simultaneously by the external bias of tunable AIs;the Darlington configuration of composite transistors provides high gain;furthermore,the adoption of the small size AIs instead of large size passive spiral inductor,and the use of composite resistors make the LNA have a small size.The LNA is fabricated and verified by GaAs/InGaP hetero-junction bipolar transistor(HBT)process.The results show that at the frequency of 7 GHz,the gain S_(21)is maximum and up to 19 dB;the S_(21)can be tuned from 17 dB to 19 dB by tuning external bias of tunable AIs,that is,the tunable amount of S_(21)is 2 dB,and similarly at 8 GHz;the tunable range of 3 dB bandwidth is 1 GHz.In addition,the gain S_(21)flatness is better than 0.4 dB under frequency from 3.1 GHz to 10.6 GHz;the size of the LNA only has 760μm×1260μm(including PADs).Therefore,the proposed strategies in the paper provide a new solution to the design of small size and reconfigurable ultra-wideband(UWB)LNA and can be used further to adjust the variations of gain and bandwidth of radio frequency integrated circuits(RFICs)due to package,parasitic and the variation of fabrication process and temperature.
文摘A CMOS variable gain amplifier(VGA) that adopts a novel exponential gain approximation is presented.No additional exponential gain control circuit is required in the proposed VGA used in a direct conversion receiver.A wide gain control voltage from 0.4 to 1.8 V and a high linearity performance are achieved.The three-stage VGA with automatic gain control(AGC) and DC offset cancellation(DCOC) is fabricated in a 0.18-μm CMOS technology and shows a linear gain range of more than 58-dB with a linearity error less than ±1 dB.The 3-dB bandwidth is over 8 MHz at all gain settings.The measured input-referred third intercept point(IIP3) of the proposed VGA varies from-18.1 to 13.5 dBm,and the measured noise figure varies from 27 to 65 dB at a frequency of 1 MHz.The dynamic range of the closed-loop AGC exceeds 56 dB,where the output signal-to-noise-and-distortion ratio(SNDR) reaches 20 dB.The whole circuit,occupying 0.3 mm^2 of chip area,dissipates less than 3.7 mA from a 1.8-V supply.
基金Project supported by the National High Technology Research and Development Program of China(No.2008AA04A 102)
文摘A differential automatic gain control (AGC) circuit is presented. The AGC architecture contains twostage variable gain amplifiers (VGAs) which are implemented with a Gilbert cell, a peak detector (PD), a low pass filter, an operational amplifier, and two voltage to current (V-I) convertors. One stage VGA achieves 30 dB gain due to the use of active load. The AGC circuit is implemented in UMC 0.18-um single-poly six-metal CMOS process technology. Measurement results show that the final differential output swing of the 2nd stage VGA is about 0.9-Vpp; the total gain of the two VGAs can be varied linearly from -10 to 50 dB when the control voltage varies from 0.3 to 0.9 V. The final circuit (containing output buffers and a band-gap reference) consumes 37 mA from single 1.8 V voltage supply. For a 50 mV amplitude 60% modulation depth input AM signal it needs 100 us to stabilize the output. The frequency response of the circuit has almost a constant -3 dB bandwidth of 2.2 MHz. Its OIP3 result is at 19 dBm.
基金supported by the National High-Tech Research and Development Program of China(Nos.2008AA010703,2009AA011606)the National Natural Science Foundation of China(No.60976023)
文摘This paper proposes a new structure to lower the power consumption of a variable gain amplifier(VGA) and keep the linearity of the VGA unchanged.The structure is used in a high rate amplitude-shift keying(ASK) based IF-stage.It includes an automatic gain control(AGC) loop and ASK demodulator.The AGC mainly consists of sixstage VGAs.The IF-stage is realized in 0.18μm CMOS technology.The measurement results show that the power consumption of the whole system is very low.The system consumes 730μA while operating at 1.8 V.The minimum ASK signal the system could detect is 0.7 mV(peak to peak amplitude).
文摘A broadband programmable gain amplifier(PGA) with a small gain step and low gain error has been designed in 0.13 m CMOS technology. The PGA was implemented with open-loop architecture to provide wide bandwidth. A two-stage gain control method, which consists of a resistor ladder attenuator and an active fine gain control stage, provides the small gain step. A look-up table based gain control method is introduced in the fine gain control stage to lower the gain error.The proposedPGAshows a decibel-linear variable gainfrom4 to20 dB with a gain step of 0.1 dB and a gain error less than˙0.05 dB. The 3-dB bandwidth and maximum IIP3 are 3.8 GHz and 17 dBm, respectively.
基金Project supported by the National High-Tech R&D Program of China(No.2009AA01Z260)the Guangdong Science and Technology Program(No.2009A010100004)Guangdong & Hong Kong Cooperation Key Area 2010(No.2010498E1)
文摘A CMOS RF front-end for the long-term evolution(LTE) direct conversion receiver is presented.With a low noise transconductance amplifier(LNA),current commutating passive mixer and transimpedance operational amplifier(TIA),the RF front-end structure enables high-integration,high linearity and simple frequency planning for LTE multi-band applications.Large variable gain is achieved using current-steering transconductance stages.A current commutating passive mixer with 25%duty-cycle LO improves gain,noise and linearity.A direct coupled current-input filter(DCF) is employed to suppress the out-of-band interferer.Fabricated in a 0.13-μm CMOS process,the RF front-end achieves a 45 dB conversion voltage gain,2.7 dB NF,-7 dBm IIP3,and +60 dBm IIP2 with calibration from 2.3 to 2.7 GHz.The total RF front end with divider draws 40 mA from a single 1.2-V supply.
基金Project supported by the National Natural Science Foundation of China(No.61376099)the Foundation for Fundamental Research of China(No.JSZL2016110B003)the Major Fundamental Research Program of Shaanxi(No.2017ZDJC-26)
文摘A 5 Gb/s adaptive equalizer with a new adaptation scheme is presented here by using 0.13μm CMOS process. The circuit consists of the combination of equalizer amplifier, limiter amplifier and adaptation loop. The adaptive algorithm exploits both the low frequency gain loop and the equalizer loop to minimize the inter-symbol interference (ISI) for a variety of cable characteristics. In addition, an offset cancellation loop is used to alleviate the offset influence of the signal path. The adaptive equalizer core occupies an area of 0.3567 mm2 and consumes a power consumption of 81.7 mW with 1.8 V power supply. Experiment results demonstrate that the equalizer could compensate for a designed cable loss with 0.23 UI peak-to-peak jitter.
文摘A wide tuning range,low power CMOS automatic gain control(AGC) with a simple architecture is proposed. The proposed AGC is composed of a variable gain amplifier(VGA),a comparator and a charge pump,and the dB-linear gain is controlled by the charge pump.The AGC was implemented in a 0.18μm CMOS technology.The dynamic range of the VGA is more than 55 dB,the bandwidth is 30 MHz,and the gain error is lower than±1.5 dB over the full temperature and gain ranges.It is designed for GPS application and is fed from a single 1.8 V power supply. The AGC power consumption is less than 5 mW,and the area of the AGC is 700×450μm^2.
基金supported by the National High Technology Research and Development Program of China(No.2009AA01Z261)the State Key Laboratory of Wireless Telecommunication,Southeast University.
文摘A wideband receiver RP front-end for IR-UWB applications is implemented in 0.13μm CMOS technology. Thanks to the direct sub-sampling architecture,there is no mixing process.Both LNA and VGA work at RF frequencies.To optimize noise as well as linearity,a differential common-source LNA with capacitive cross- coupling is used,which only consumes current of 1.8 mA from a 1.2 V power supply.Following LNA,a two-stage current-steering VGA is adopted for gain tuning.To extend the overall bandwidth,a three-stage staggered peaking technique is used.Measurement results show that the proposed receiver front-end achieves a gain tuning range from 5 to 40 dB within 6-7 GHz,a minimum noise figure of 4.5 dB and a largest IIP_3 of-11 dBm.The core receiver (without test buffer) consumes 14 mW from a 1.2 V power supply and occupies 0.58 mm^2 area.
基金supported by the Technology Major Project(No.2012ZX03004007-002)the National Natural Science Foundation of China(No. 60976023)the National Key Technology Research and Development Program of the Ministry of Science and Technology of China (No.2012BAH20B02)
文摘This paper presents a low power 2.4 GHz transceiver for ZigBee applications.This transceiver adopts low power system architecture with a low-IF receiver and a direct-conversion transmitter.The receiver consists of a new low noise amplifier(LNA) with a noise cancellation function,a new inverter-based variable gain complex filter (VGCF) for image rejection,a passive quadrature mixer,and a decibel linear programmable gain amplifier(PGA). The transmitter adopts a quadrature mixer and a class-B mode variable gain power amplifier(PA) to reduce power consumption.This transceiver is implemented in 0.18μm CMOS technology.The receiver achieves—95 dBm of sensitivity,28 dBc of image rejection,and -8 dBm of third-order input intercept point(IIP3).The transmitter can deliver a maximum of+3 dBm output power with PA efficiency of 30%.The whole chip area is less than 4.32 mm^2. It only consumes 12.63 mW in receiving mode and 14.22 mW in transmitting mode,respectively.
基金supported by the National Natural Science Foundation of China (Nos. 61234002, 61322405, 61306044, 61376033)the National High-Tech Program of China (No. 2013AA014103)the Opening Project of Science and Technology on Reliability Physics and Application Technology of Electronic Component Laboratory (No. ZHD201302)
文摘A 14-bit,40-MHz analog front end(AFE) for CCD scanners is analyzed and designed.The proposed system incorporates a digitally controlled wideband variable gain amplifier(VGA) with nearly 42 dB gain range,a correlated double sampler(CDS) with programmable gain functionality,a 14-bit analog-to-digital converter and a programmable timing core.To achieve the maximum dynamic range,the VGA proposed here can linearly amplify the input signal in a gain range from-1.08 to 41.06 dB in 6.02 dB step with a constant bandwidth.A novel CDS takes image information out of noise,and further amplifies the signal accurately in a gain range from 0 to 18 dB in0.035 dB step.A 14-bit ADC is adopted to quantify the analog signal with optimization in power and linearity.An internal timing core can provide flexible timing for CCD arrays,CDS and ADC.The proposed AFE was fabricated in SMIC 0.18 μm CMOS process.The whole circuit occupied an active area of 2.8×4.8 mm^2 and consumed360 mW.When the frequency of input signal is 6.069 MHz,and the sampling frequency is 40 MHz,the signal to noise and distortion(SNDR) is 70.3 dB,the effective number of bits is 11.39 bit.