Effects of back gate bias on radio-frequency performance in partially depleted silicon-on-inslator nMOSFETs

The effects of back gate bias(BGEs) on radio-frequency(RF) performances in PD SOI n MOSFETs are presented in this paper. Floating body(FB) device, T-gate body-contact(TB) device, and tunnel diode body-contact(TDBC) device, of which the supply voltages are all 1.2 V, are compared under different back gate biases by different figures of merit, such as cut-off frequency( fT), maximum frequency of oscillation( fmax), etc. Because of the lack of a back gate conducting channel, the drain conductance(gd) of TDBC transistor shows a smaller degradation than those of the others, and the trans-conductance(gm) of TDBC is almost independent of back gate bias. The values of fT of TDBC are also kept nearly constant under different back gate biases. However, RF performances of FB and TB each show a significant degradation when the back gate bias is larger than ～ 20 V. The results indicate that TDBC structures could effectively improve the back gate bias in RF performance.

Impact of back-gate bias on the hysteresis effect in partially depleted SOI MOSFETs

The hysteresis effect in the output characteristics,originating from the floating body effect,has been measured in partially depleted（PD） silicon-on-insulator（SOI） MOSFETs at different back-gate biases.I D hysteresis has been developed to clarify the hysteresis characteristics.The fabricated devices show the positive and negative peaks in the I D hysteresis.The experimental results show that the I D hysteresis is sensitive to the back gate bias in 0.13-渭m PD SOI MOSFETs and does not vary monotonously with the back-gate bias.Based on the steady-state Shockley-Read-Hall（SRH） recombination theory,we have successfully interpreted the impact of the back-gate bias on the hysteresis effect in PD SOI MOSFETs.

The origin of gate bias stress instability and hysteresis in monolayer WS2 transistors

Due to the ultra-thin nature and moderate carrier mobility,semiconducting two-dimensional(2D)materials have attracted extensive attention for next-generation electronics.However,the gate bias stress instability and hysteresis are always observed in these 2D materials-based transistors that significantly degrade their reliability for practical applications.Herein,the origin of gate bias stress instability and hysteresis for chemical vapor deposited monolayer WS2 transistors are investigated carefully.The transistor performance is found to be strongly affected by the gate bias stress time,sweeping rate and range,and temperature.Based on the systematical study and complementary analysis,charge trapping is determined to be the major contribution for these observed phenomena.Importantly,due to these charge trapping effects,the channel current is observed to decrease with time;hence,a rate equation,considering the charge trapping and time decay effect of current,is proposed and developed to model the phenomena with excellent consistency with experimental data.All these results do not only indicate the validity of the charge trapping model,but also confirm the hysteresis being indeed caused by charge trapping.Evidently,this simple model provides a sufficient explanation for the charge trapping induced gate bias stress instability and hysteresis in monolayer WS2 transistors,which can be also applicable to other kinds of transistors.

Positive Bias Temperature Instability and Hot Carrier Injection of Back Gate Ultra-thin-body In0.53Ga0.47As-on-Insulator n-Channel Metal-Oxide-Semiconductor Field-Effect Transistor

Ultra-thin-body （UTB） In0.53Ga0.47As-on-insulator （In0.53Ga0.47As-OI） structures with thicknesses of 8 and 15nm are realized by transferring epitaxially grown In0.53Ga0.47As layers to silicon substrates with 15-nmthick A12 03 as a buried oxide by using the direct wafer bonding method. Back gate n-channel metal-oxidesemiconductor field-effect transistors （nMOSFETs） are fabricated by using these In0.53Ga0.47As-OI structures with excellent electrical characteristics. Positive bias temperature instability （PBTI） and hot carrier injection （HCI） characterizations are performed for the In0.53Ga0.47As-OI nMOSFETs. It is confirmed that the In0.53Ga0.47 As-OI nMOSFETs with a thinner body thickness suffer from more severe degradations under both PBTI and HCr stresses. Moreover, the different evolutions of the threshold voltage and the saturation current of the UTB In0.53Ga0.47As-OI nMOSFETs may be due to the slow border traps.

Evaluation of stress voltage on off-state time-dependent breakdown for GaN MIS-HEMT with SiNx gate dielectric

Stress voltages on time-dependent breakdown characteristics of GaN MIS-HEMTs during negative gate bias stress (with VGS < 0, VD = VS = 0) and off-state stress (VG < VTh, VDS > 0, VS = 0) are investigated. For negative bias stress, the breakdown time distribution (β) decreases with the increasing negative gate voltage, while β is larger for higher drain voltage at off-state stress. Two humps in the time-dependent gate leakage occurred under both breakdown conditions, which can be ascribed to the dielectric breakdown triggered earlier and followed by the GaN layer breakdown. Combining the electric distribution from simulation and long-term monitoring of electric parameter, the peak electric fields under the gate edges at source and drain sides are confirmed as the main formation locations for per-location paths during negative gate voltage stress and off-state stress, respectively.

基于高摆率误差放大器的低功耗LDO设计

本文设计了一种具有低静态电流的低压差线性稳压器(LDO).针对传统LDO在低静态电流下瞬态响应不足的问题,电路中的误差放大器采用两个共栅差分跨导单元交叉耦合连接进行设计,提高其压摆率;利用体偏置运放改变功率管的阈值电压实现功率管在不同负载的快速切换;同时采用动态偏置对电路进行偏置减少过欠冲值.电路采用台积电(TSMC)0.18µm互补金属氧化物半导体(CMOS)工艺进行设计,版图核心面积为220µm×140µm.仿真结果表明,该LDO在最小负载电流与最大负载电容的组合下相位裕度达到100度,消耗的静态电流仅为849 nA.当负载电流在500 ns时间内从100µA到100 mA进行切换时,电路表现出良好的瞬态响应,其中过冲电压为220 mV,欠冲电压为225 mV.经过计算,品质因数(FOM)值为0.198 mV.

自保护MOS栅晶闸管

本文报告一种叫做自保护MOS栅晶闸管的新器件 .这种器件无寄生闩锁效应 ,并在较高阳极电压下展现出电流下降而不是饱和或上升的特性 .因此 ,这种新器件具有令人满意的正偏安全工作区 .器件的保护点由用户外接输入电阻自行调节 ,极大增加了使用的灵活性 .此外 ,器件保护点电流和电压的温度系数均为负 。

增强型GaN MOSFET的制备及其绝缘栅的电荷特性研究

采用ICP干法刻蚀和PECVD沉积技术,制备了增强型Si衬底SiO2/GaN MOS栅场效应晶体管(MOSFET)。SiO2/GaN MOSFET转移特性曲线测试中出现阈值电压不稳定现象,针对其阈值电压稳定性问题,采用正向电压偏置方法对SiO2/GaN MOSFET的绝缘栅电荷特性展开研究。正向电压偏置后,器件的转移特性曲线和高频C-V特性曲线均正向偏移,研究表明:SiO2/GaN之间存在的界面态和靠近SiO2/GaN界面的SiO2内部陷阱是造成SiO2/GaN MOSFET阈值电压不稳定的原因,实验研究结果同时表明氮气1 000℃快速热退火(RTA)对SiO2内部陷阱有改善作用。

基于动态栅压功放的高效超宽带发射机结构

提出的超宽带射频发射机的结构具有良好的效率和线性度。设计和制作了一款宽带的动态栅压偏置的功率放大器。动态栅压偏置可以获得优良的宽带性能。总发射机可以支持184.32 MHz的调制带宽。基带信号和相关偏置电压由宽带模拟基带处理单元生成。基带信号经过直接变频的调制方式到达功放输入端,偏置电压经过差分运放以及延时电路到达功放栅极。实验结果表明,与传统A类功放相比,动态栅压偏置可以增加系统的效率和线性度。

基于沟长偏置的近阈值逻辑漏功耗减小技术

随着集成电路芯片特征尺寸的不断缩小,减小漏功耗已成为集成电路设计技术的焦点之一.在近阈值逻辑电路中,亚阈值漏电流是其最主要漏电流的构成.根据MOS器件沟道长度与亚阈值漏电流之间的非线性关系,通过适度提高MOS器件的沟道长度从而降低CMOS逻辑电路的漏功耗,形成了基于沟长偏置的漏功耗减小技术.应用HSPICE软件对基于45nm PTM工艺参数沟长偏置为8%的基本逻辑门电路、镜像加法器和传输门加法器的漏电流进行了仿真测试,实验结果表明漏电流约下降了39%～44%.因此沟长偏置技术是一种有效的适用于近阈值逻辑的漏功耗减小技术.

一种自偏置预失真线性功率放大器

该文提出了一种用中芯国际0.18μm工艺设计的自偏置预失真AB类功率放大电路电路结构。电路采用两级共源共栅结构,在共栅MOS管上采用自偏置电路,在第二级电路中采用预失真电路。该次设计采用Agilent的ADS软件对电路进行模拟,在2.4GHz频率下,1dB压缩点的输出功率为22.5dBm,此时的PAE是25.1%。

SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey

Low power supply operation with leakage power reduction is the prime concern in modern nano-scale CMOS memory devices. In the present scenario, low leakage memory architecture becomes more challenging, as it has 30% of the total chip power consumption. Since, the SRAM cell is low in density and most of memory processing data remain stable during the data holding operation, the stored memory data are more affected by the leakage phenomena in the circuit while the device parameters are scaled down. In this survey, origins of leakage currents in a short-channel device and various leakage control techniques for ultra-low power SRAM design are discussed. A classification of these approaches made based on their key design and functions, such as biasing technique, power gating and multi-threshold techniques. Based on our survey, we summarize the merits and demerits and challenges of these techniques. This comprehensive study will be helpful to extend the further research for future implementations.

65nm CMOS工艺中的高速多标准FPGA I/O接口设计

设计了一种现场可编程门阵列(FPGA)中使用的高速可配置的输入输出(I/O)接口电路。通过使用电平移位电路、互补自偏置差分放大电路(CSDA)等,该电路实现了包括低压差分信号(LVDS)在内的多种常见的接口协议标准。该电路同时具备可编程配置压摆率和可编程配置输出驱动电流的功能,同时为保证信号完整性,设计了数字阻抗匹配(DCI)模块。芯片使用SMIC 1P10M65nm CMOS工艺流片。测试结果表明,芯片核心电路在1.2V电压下能保证各种协议工作正常,输入输出信号延时、最大输出电流、最高工作速率等与仿真结果吻合,均达到设计指标要求。

具有宽安全工作区的压接式IGBT芯片研制

针对柔性直流输电关键装备高压直流断路器的特殊需求,基于现有工艺平台开发了一款宽安全工作区的3 300V/50A压接式IGBT芯片。为降低2~4 ms过电流冲击过程中的芯片温升,纵向采用非穿通结构。同时,采用阶梯栅氧结构,引入第二雪崩区,降低动态闩锁发生的风险,提高器件的安全工作区。为适用于压接封装,开发了厚金属电极工艺,实现对压力的缓冲。将此结构流片验证,并进行模块级测试,芯片可在1 800V电压下达到6.5倍以上额定电流安全关断,短路电流可在20μs内安全关断,具有宽安全工作区水平。

Characterization of positive bias temperature instability of NMOSFET with high-k/metal gate last process

Positive bias temperature instability（PBTI） characteristics and degradation mechanisms of NMOSFET with high-k/metal gate last process have been systematically investigated. The time evolution of threshold voltage shift during PBTI stress still follows a power law. However, the exponent n decreases from 0.26 to 0.16 linearly as the gate stress voltage increases from 0.6 to 1.2 V. There is no interface state generation during stress because of the negligible sub-threshold swing change. Moreover, the activation energy is 0.1 e V, which implies that electrons directly tunnel into high-k bulk and are trapped by pre-existing traps resulting into PBTI degradation. During recovery the threshold voltage shift is linear in lgt, and a mathematical model is proposed to express threshold voltage shift.

有源电压箝位串联HV IGBT的适用性和优化(二)

介绍了5.2kV高压绝缘栅双极型晶体管(HVIGBTs)的成功串联应用。穿通型HVIGBT串联应用时要完全控制感应过电压,最大的障碍是拖尾电流的关断问题。可以证明,采用先进的电压箝位技术能够限制因关断拖尾电流而引起的第二个电压尖峰。阳极采用载流子寿命局部分布的IGBT很适合这种应用;拖尾电流间隔时间越短,关断损耗越小。文中集中讨论了穿通型HVIGBT器件串联时的最佳通态等离子体分布,HVIGBT的最新发展趋势似乎与讨论结论相一致。未来先进的HVIGBT技术可完全减轻第一代HVIGBT串联时的困难。

有源电压箝位串联HV IGBT的适用性和优化(一)

介绍了5.2kV高压绝缘栅双极型晶体管(HV IGBTs)的成功串联应用。穿通型HV IGBT串联应用时要完全控制感应过电压,最大的障碍是拖尾电流的关断问题。可以证明,采用先进的电压箝位技术能够限制因关断拖尾电流而引起的第二个电压尖峰。阳极采用载流子寿命局部分布的IGBT很适合这种应用;拖尾电流间隔时间越短,关断损耗越小。文中集中讨论了穿通型HV IGBT器件串联时的最佳通态等离子体分布,HV IGBT的最新发展趋势似乎与讨论结论相一致。未来先进的HV IGBT技术可完全减轻第一代HV IGBT串联时的困难。