On modeling the digital gate delay under process variation

To achieve a characterization method for the gate delay library used in block based statistical static timing analysis with neither unacceptably poor accuracy nor forbiddingly high cost,we found that general-purpose gate delay models are useful as intermediaries between the circuit simulation data and the gate delay models in required forms.In this work,two gate delay models for process variation considering different driving and loading conditions are proposed.From the testing results,these two models,especially the one that combines effective dimension reduction（EDR） from statistics society with comprehensive gate delay models,offer good accuracy with low characterization cost,and they are thus competent for use in statistical timing analysis（SSTA）.In addition, these two models have their own value in other SSTA techniques.

Controllable all-optical stochastic logic gates and their delay storages based on the cascaded VCSELs with optical-injection

Using the dynamical properties of the polarization bistability that depends on the detuning of the injected light,we propose a novel approach to implement reliable all-optical stochastic logic gates in the cascaded vertical cavity surface emitting lasers（VCSELs） with optical-injection.Here,two logic inputs are encoded in the detuning of the injected light from a tunable CW laser.The logic outputs are decoded from the two orthogonal polarization lights emitted from the optically injected VCSELs.For the same logic inputs,under electro-optic modulation,we perform various digital signal processing（NOT,AND,NAND,XOR,XNOR,OR,NOR） in the all-optical domain by controlling the logic operation of the applied electric field.Also we explore their delay storages by using the mechanism of the generalized chaotic synchronization.To quantify the reliabilities of these logic gates,we further demonstrate their success probabilities.

Fin Field Effect Transistor with Active 4-Bit Arithmetic Operations in 22 nm Technology

A design of a high-speed multi-core processor with compact size is a trending approach in the Integrated Circuits(ICs)fabrication industries.Because whenever device size comes down into narrow,designers facing many power den-sity issues should be reduced by scaling threshold voltage and supply voltage.Initially,Complementary Metal Oxide Semiconductor(CMOS)technology sup-ports power saving up to 32 nm gate length,but further scaling causes short severe channel effects such as threshold voltage swing,mobility degradation,and more leakage power(less than 32)at gate length.Hence,it directly affects the arithmetic logic unit(ALU),which suffers a significant power density of the scaled multi-core architecture.Therefore,it losses reliability features to get overheating and increased temperature.This paper presents a novel power mini-mization technique for active 4-bit ALU operations using Fin Field Effect Tran-sistor(FinFET)at 22 nm technology.Based on this,a diode is directly connected to the load transistor,and it is active only at the saturation region as a function.Thereby,the access transistor can cutoff of the leakage current,and sleep transis-tors control theflow of leakage current corresponding to each instant ALU opera-tion.The combination of transistors(access and sleep)reduces the leakage current from micro to nano-ampere.Further,the power minimization is achieved by con-necting the number of transistors(6T and 10T)of the FinFET structure to ALU with 22 nm technology.For simulation concerns,a Tanner(T-Spice)with 22 nm technology implements the proposed design,which reduces threshold vol-tage swing,supply power,leakage current,gate length delay,etc.As a result,it is quite suitable for the ALU architecture of a high-speed multi-core processor.

地质雷达测控系统的FPGA实现

超宽带地质雷达测控系统的关键是等效时间采样系统的实现,而等效时间采样需要一个精确的可编程延时器。利用Cyclone III、IV的锁相环(PLL)模块的动态相位调整功能,实现了最小步长125 ps的可编程延时器,可完成高达8 GS/s的等效采样,并开发了相应的测控模块。测控模块通过Avalon总线与软核NIOS II连接,在NIOS II的控制下实现地质雷达的扫描控制。该设计具有结构紧凑、性能稳定、成本低廉等优点,适用于低频段地质雷达。试验测试证明了系统的可行性。