Direct Tunneling Currents Through Gate Dielectrics in Deep Submicron MOSFETs

A direct tunneling model through gate dielectric s in CMOS devices in the frame of WKB approximation is reported.In the model,an im proved one-band effective mass approximation is used for the hole quantization, where valence band mixing is taken into account.By comparing to the experiments, the model is demonstrated to be applicable to both electron and hole tunneling c urrents in CMOS devices.The effect of the dispersion in oxide energy gap on the tunneling current is also studied.This model can be further extended to study th e direct tunneling current in future high-k materials.

Energy-band alignment of atomic layer deposited(HfO_2)_x(Al_2O_3)_(1-x) gate dielectrics on 4H-SiC

We study a series of（HfO2）x（Al2O3）1-x /4H-SiC MOS capacitors. It is shown that the conduction band offset of HfO2 is 0.5 e V and the conduction band offset of Hf AlO is 1.11–1.72 e V. The conduction band offsets of（Hf O2）x（Al2O3）1-x are increased with the increase of the Al composition, and the（HfO2）x（Al2O3）1-x offer acceptable barrier heights（〉 1 e V）for both electrons and holes. With a higher conduction band offset,（Hf O2）x（Al2O3）1-x/4H-SiC MOS capacitors result in a ～ 3 orders of magnitude lower gate leakage current at an effective electric field of 15 MV/cm and roughly the same effective breakdown field of ～ 25 MV/cm compared to HfO2. Considering the tradeoff among the band gap, the band offset, and the dielectric constant, we conclude that the optimum Al2O3 concentration is about 30% for an alternative gate dielectric in 4H-Si C power MOS-based transistors.

Phase control of magnetron sputtering deposited Gd_2O_3 thin films as high-κ gate dielectrics

Gd2O3 thin films as high-κ gate dielectrics were deposited directly on Si（001） substrates by magnetron sputtering at a pressure of 1.3 Pa and different temperatures. X-ray diffraction results revealed that all the films grown from 450 to 570 ℃ were crystalline, and the Gd2O3 thin films consisted of a mixture of cubic and monoclinic phases. The growth temperature was a critical parameter for the phase constituents and their relative amount. Low temperature was favorable for the formation of cubic phase while higher temperature gave rise to more monoclinic phase. All the Gd2O3 thin films grown from different temperatures exhibited acceptable electrical properties, such as low leakage current density （JL） of 10-5 A/cm^2 at zero bias with capacitance equivalent SiO2 thickness in the range of 6-13 nm. Through the comparison between films grown at 450 and 570 ℃, the existence of monoclinic phase caused an increase in JL by nearly one order of magnitude and a reduction of effective dielectric constant from 17 to 9.

The influence and explanation of fringing-induced barrier lowering on sub-100 nm MOSFETs with high-k gate dielectrics

The fringing-induced barrier lowering（FIBL） effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator.An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect.The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance.Based on equivalent capacitance theory,the influences of channel length,junction depth,gate/lightly doped drain（LDD） overlap length,spacer material and spacer width on FIBL is thoroughly investigated.A stack gate dielectric is presented to suppress the FIBL effect.

Current-collapse suppression and leakage-current decrease in AlGaN/GaN HEMT by sputter-TaN gate-dielectric layer

In this paper, we explore the electrical characteristics of high-electron-mobility transistors(HEMTs) using a TaN/AlGaN/GaN metal insulating semiconductor(MIS) structure. The high-resistance tantalum nitride(TaN) film prepared by magnetron sputtering as the gate dielectric layer of the device achieved an effective reduction of electronic states at the TaN/AlGaN interface, and reducing the gate leakage current of the MIS HEMT, its performance was enhanced. The HEMT exhibited a low gate leakage current of 2.15 × 10^(-7) mA/mm and a breakdown voltage of 1180 V. Furthermore, the MIS HEMT displayed exceptional operational stability during dynamic tests, with dynamic resistance remaining only 1.39 times even under 400 V stress.

Aqueous-solution-driven HfGdO_x gate dielectrics for low-voltage-operated α-InGaZnO transistors and inverter circuits

In this work,a non-toxic and environmentally friendly aqueous-solution-based method has been adopted to prepare gadolinium-doped hafnium oxide(HfO2) gate dielectric thin films.By adjusting the gadolinium(Gd) doping concentration,the oxygen vacancy content,band offset,interface trap density,and dielectric constant of HfGdOx(HGO) thin films have been optimized.Results have confirmed that HGO thin films with Gd doping ratio of 15 at.% have demonstrated appropriate dielectric constant of 27.1 and lower leakage current density of 5.8×10-9 A cm-2.Amorphous indium-gallium-zinc oxide(α-IGZO) thin film transistors(TFTs) based on HGO thin film(Gd:15 at.%) as gate dielectric layer have exhibited excellent electrical performance,such as larger saturated carrier mobility(μsat) of 20.1 cm2 V-1 S-1,high on/off current ratio(Ion/Ioff) of ~108,smaller sub-threshold swing(SS) of 0.07 V decade-1,and a negligible threshold voltage shift(ΔVTH) of 0.08 V under positive bias stress(PBS) for 7200 s.To confirm its potential application in logic circuit,a resistor-loaded inverter based on HGO/α-IGZO TFTs has been constructed.A high voltage gain of 19.8 and stable full swing characteristics have been detected.As a result,it can be concluded that aqueous-solution-driven HGO dielectrics have potential application in high resolution flat panel displays and ultra-large-scale integrated logic circuits.

Challenges in Atomic-Scale Characterization of High-k Dielectrics and Metal Gate Electrodes for Advanced CMOS Gate Stacks

The decreasing feature sizes in complementary metal-oxide semiconductor （CMOS） transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant （high-k） because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability. In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology. Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties. It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling. In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices. Therefore, detailed atomic- scale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks, are highly required. In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed. Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy （HRTEM） and the related techniques based on scanning transmission electron microscopy （STEM）, including high-angle annular dark- field （HAADF） imaging （also known as Z-contrast imaging）, electron energy-loss spectroscopy （EELS）, and energy dispersive X-ray spectroscopy （EDS）, due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric gate stacks in the present and future generations of CMOS devices. In Section 1 of this review, the working principles of each technique are briefly introduced and their key features are outlined. In Section 2, microstructural characterizations of high-k gate dielectrics at atomic-scale by electron microscopy are critically reviewed by citing some recent results reported on high-k gate dielectrics. In Section 3, metal gate electrodes and the interfacial structures between high-k dielectrics and metal gates are discussed. The electron beam damage effects in high-k gate stacks are also evaluated, and their origins and prevention are described in Section 4. Finally, we end this review with personal perspectives towards the future challenges of atomic-scale material characterization in advanced CMOS gate stacks.

A Microwave High Power Static Induction Transistor with Double Dielectrics Gate Structure

The designing approaches and key fabricating technologies for high frequency high power double dielectrics gate static induction transistor (DDG SIT) with mixed non-saturating I-V characteristics are presented.The effects of parasitic gate-source capacitance (C gs) on the power performance of SIT are discussed.The main methods and considerations to diminish C gs,consequently to improve the high power performance are given.Synchronous epitaxy technology is the critical step to decrease C gs.The 7-μm pitch DDG SIT delivering output power >20W with >7dB power gain and >70% drain efficiency at 400MHz,and delivering output power >7W with >5dB power gain and >50% drain efficiency at 700MHz are successfully fabricated.

Novel electrical characterization for advanced CMOS gate dielectrics

This paper reviews the following electrical characterization techniques for measuring the microscopic bonding structures, impurities, and electrically active defects in advanced CMOS gate stacks： 1） inelastic electron tunneling spectroscopy （IETS）, 2） lateral profiling of threshold voltages, interface-trap density, and oxide charge density distributions along the channel of an MOSFET, and 3） pulse agitated substrate hot electron injection （PASHEI） technique for measuring trapping effects in the gate dielectric at low and modest gate voltages.

High-performance enhancement-mode AlGaN/GaN MOS-HEMTs with fluorinated stack gate dielectrics and thin barrier layer

We present high-performance enhancement-mode AlGaN/GaN metal-oxide-semiconductor highelectron mobility transistors（MOS-HEMTs） by a fluorinated gate dielectric technique.A nanolaminate of an Al_2O_3/La_xAl_（1-x）O_3/Al_2O_3 stack（x≈0.33） grown by atomic layer deposition is employed to avoid fluorine ions implantation into the scaled barrier layer.Fabricated enhancement-mode MOS-HEMTs exhibit an excellent performance as compared to those with the conventional dielectric-last technique,delivering a large maximum drain current of 916 mA/mm and simultaneously a high peak transconductance of 342 mS/mm.The balanced DC characteristics indicate that advanced gate stack dielectrics combined with buffered fluorine ions implantation have a great potential for high speed GaN E/D-mode integrated circuit applications.

Electrical Properties of Ultra Thin Nitride/Oxynitride Stack Dielectrics pMOS Capacitor with Refractory Metal Gate

Electrical properties of high quality ultra thin nitride/oxynitride(N/O)stack dielectrics pMOS capacitor with refractory metal gate electrode are investigated,and ultra thin (<2 nm) N/O stack gate dielectrics with significant low leakage current and high resistance to boron penetration are fabricated.Experiment results show that the stack gate dielectric of nitride/oxynitride combined with improved sputtered tungsten/titanium nitride (W/TiN) gate electrode is one of the candidates for deep sub-micron metal gate CMOS devices.

Characterization of Sub-100nm MOSFETs with High K Gate Dielectric

The short-channel performance of typical 70nm MOSFETs with high K gate dielectric is widely studied by using a two dimensional(2-D) device simulator.The short-channel performance is degraded from the fringing field and lower the source/drain junction resistance.The sidewall material is found very useful to eliminate the fringing-induced berrier lowing effect.

Gate Current for MOSFETs with High k Dielectric Materials

The MOSFET gate currents of high k gate dielectrics due to direct tunneling are investigated by using a new direct tunneling current model developed.The model includes both the inversion layer quantization effect with finite barrier height and the polysilicon depletion effect.The impacts of dielectric constant and conduction band offset as well as the band gap on the gate current are discussed.The results indicate that the gate dielectric materials with higher dielectric constant,larger conduction band offset and the larger band gap are necessary to reduce the gate current.The calculated results can be used as a guide to select the appropriate high k gate dielectric materials for MOSFETs.

Characterization of Gate Dielectric Using Oxides Generated by in situ Steam Generation

A new process for gate dielectric fabrication named in situ steam generation （ISSG） is reported. Based on the Deal-Grove model, an oxidation mechanism is proposed to break the Si- Si bond by an active atomic O and form a Si- O - Si bond during the oxidation process. The breakdown characteristics are investigated through a MOS-capacitor for both ISSG and furnace wet oxidation. The gate dielectric material generated by ISSG oxidation has a superior electrical performance owing to sufficient oxidation of weak Si-Si bonds relative to furnace wet oxidation,indicating a promising application in sub-micron IC device manufacturing.

A High Performance Sub-100nm Nitride/Oxynitride Stack Gate Dielectric CMOS Device with Refractory W/TiN Metal Gates

By complementing the equivalent oxide thickness （EOT） of a 1.7nm nitride/oxynitride （N/O） stack gate dielectric （EOT- 1.7nm） with a W/TiN metal gate electrode,metal gate CMOS devices with sub-100nm gate length are fabricated in China for the first time. The key technologies adopted to restrain SCE and to improve drive ability include a 1.7nm N/O stack gate dielectric, non-CMP planarization technology, a T-type refractory W/TiN metal stack gate electrode, and a novel super steep retrograde channel doping using heavy ion implantation and a double sidewall scheme. Using these optimized key technologies, high performance 95nm metal gate CMOS devices with excellent SCE and good driving ability are fabricated. Under power supply voltages of VDS ± 1.5V and VGS± 1.8V,drive currents of 679μA/μm for nMOS and - 327μA/μm for pMOS are obtained. A subthreshold slope of 84.46mV/dec, DIBL of 34.76mV/V, and Vth of 0.26V for nMOS, and a subthreshold slope of 107.4mV/dec,DIBL of 54.46mV/V, and Vth of 0.27V for pMOS are achieved. These results show that the combined technology has indeed thoroughly eliminated the boron penetration phenomenon and polysilicon depletion effect ,effectively reduced gate tunneling leakage, and improved device reliability.

Fabrication of Ultrathin SiO_2 Gate Dielectric by Direct Nitrogen Implantation into Silicon Substrate

Nitrogen implantation in silicon substrate at fixed energy of 35keV and split dose of 10 14～5×10 14cm -2 is performed before gate oxidation.The experiment results indicate that with the increasing of implantation dose of nitrogen,oxidation rate of gate decreases.The retardation in oxide growth is weakened due to thermal annealing after nitrogen implantation.After nitrogen is implanted at the dose of 2×10 14cm -2,initial O 2 injection method which is composed of an O 2 injection/N 2 annealing/main oxidation,is applied for preparation of 3 4nm gate oxide.Compared with the control process,which is composed of N 2 annealing/main oxidation,initial O 2 injection process suppresses leakage current of the gate oxide.But Q bd and HF C-V characteristics are almost identical for the samples fabricated by two different oxidation processes.

Characteristics of high-quality HfSiON gate dielectric prepared by physical vapour deposition

This paper presents a method using simple physical vapour deposition to form high-quality hafnium silicon oxynitride （HfSiON） on ultrathin SiO2 buffer layer. The gate dielectric with 10A （1A = 0.1 nm） equivalent oxide thickness is obtained. The experimental results indicate that the prepared HfSiON gate dielectric exhibits good physical and electrical characteristics, including very good thermal stability up to 1000℃, excellent interface properties, high dielectric constant （k = 14） and low gate-leakage current （Ig = 1.9 × 10^-3 A/cm^2@Vg = Vfb - 1 V for EOT of 10 A）. TaN metal gate electrode is integrated with the HfSiON gate dielectric.The effective work function of TaN on HfSiON is 4.3 eV, meeting the requirements of NMOS for the metal gate. And, the impacts of sputtering ambient and annealing temperature on the electrical properties of HfSiON gate dielectric are investigated.

Electrical properties and reliability of HfO2 gate-dielectric MOS capacitors with trichloroethylene surface pretreatment

Trichloroethylene （TCE） pretreatment of Si surface prior to HfO2 deposition is employed to fabricate HfO2 gatedielectric MOS capacitors. Influence of this processing procedure on interlayer growth, HfO2/Si interface properties, gate-oxide leakage and device reliability is investigated. Among the surface pretreatments in NH3, NO, N2O and TCE ambients, the TCE pretreatment gives the least interlayer growths the lowest interface-state density, the smallest gate leakage and the highest reliability. All these improvements should be ascribed to the passivation effects of Cl2 and HC1 on the structural defects in the interlayer and at the interface, and also their gettering effects on the ion contamination in the gate dielectric.

High-k gate dielectric GaAs MOS device with LaON as interlayer and NH_3-plasma surface pretreatment

High-k gate dielectric Hf Ti ON Ga As metal-oxide–semiconductor（MOS） capacitors with La ON as interfacial passivation layer（IPL） and NH3- or N2-plasma surface pretreatment are fabricated, and their interfacial and electrical properties are investigated and compared with their counterparts that have neither La ON IPL nor surface treatment. It is found that good interface quality and excellent electrical properties can be achieved for a NH3-plasma pretreated Ga As MOS device with a stacked gate dielectric of Hf Ti ON/La ON. These improvements should be ascribed to the fact that the NH3-plasma can provide H atoms and NH radicals that can effectively remove defective Ga/As oxides. In addition, La ON IPL can further block oxygen atoms from being in-diffused, and Ga and As atoms from being out-diffused from the substrate to the high-k dielectric. This greatly suppresses the formation of Ga/As native oxides and gives rise to an excellent high-k/Ga As interface.

Current Progress of Hf(Zr)-Based High-k Gate Dielectric Thin Films

With the continued downscaling of complementary metal-oxide-semiconductor field effect transistor dimensions, high-dielectric constant （high-k） gate materials, as alternatives to SiO2, have been extensively investigated. Hf （Zr）-based high-k gate dielectric thin films have been regarded as the most promising candidates for high-k gate dielectric according to the International Technology Roadmap for Semiconductor due to their excellent physical properties and performance. This paper reviews the recent progress on Hf （Zr）-based high-k gate dielectrics based on PVD （physical vapor deposition） process. This article begins with a survey of various methods developed for generating Hf （Zr）-based high-k gate dielectrics, and then mainly focuses on microstructure, synthesis, characterization, formation mechanisms of interfacial layer, and optical properties of Hf （Zr）-based high-k gate dielectrics. Finally, this review concludes with personal perspectives towards future research on Hf （Zr）-based high-k gate dielectrics.