The impacts of shallow trench isolation(STI)indium implantation on gate oxide and device characteristics are studied in this work.The stress modulation effect is confirmed in this research work.An enhanced gate oxide ...The impacts of shallow trench isolation(STI)indium implantation on gate oxide and device characteristics are studied in this work.The stress modulation effect is confirmed in this research work.An enhanced gate oxide oxidation rate is observed due to the enhanced tensile stress,and the thickness gap is around 5%.Wafers with and without STI indium implantation are manufactured using the 150-nm silicon on insulator(SOI)process.The ramped voltage stress and time to breakdown capability of the gate oxide are researched.No early failure is observed for both wafers the first time the voltage is ramped up.However,a time dependent dielectric breakdown(TDDB)test shows more obvious evidence that the gate oxide quality is weakened by the STI indium implantation.Meanwhile,the device characteristics are compared,and the difference between two devices is consistent with the equivalent oxide thickness(EOT)gap.展开更多
A split-gate SiC trench gate MOSFET with stepped thick oxide, source-connected split-gate(SG), and p-type pillar(ppillar) surrounded thick oxide shielding region(GSDP-TMOS) is investigated by Silvaco TCAD simulations....A split-gate SiC trench gate MOSFET with stepped thick oxide, source-connected split-gate(SG), and p-type pillar(ppillar) surrounded thick oxide shielding region(GSDP-TMOS) is investigated by Silvaco TCAD simulations. The sourceconnected SG region and p-pillar shielding region are introduced to form an effective two-level shielding, which reduces the specific gate–drain charge(Q_(gd,sp)) and the saturation current, thus reducing the switching loss and increasing the short-circuit capability. The thick oxide that surrounds a p-pillar shielding region efficiently protects gate oxide from being damaged by peaked electric field, thereby increasing the breakdown voltage(BV). Additionally, because of the high concentration in the n-type drift region, the electrons diffuse rapidly and the specific on-resistance(Ron,sp) becomes smaller.In the end, comparing with the bottom p~+ shielded trench MOSFET(GP-TMOS), the Baliga figure of merit(BFOM,BV~2/R_(on,sp)) is increased by 169.6%, and the high-frequency figure of merit(HF-FOM, R_(on,sp) × Q_(gd,sp)) is improved by310%, respectively.展开更多
Degradation induced by the negative bias temperature instability(NBTI)can be attributed to three mutually uncoupled physical mechanisms,i.e.,the generation of interface traps(ΔV_(IT)),hole trapping in pre-existing ga...Degradation induced by the negative bias temperature instability(NBTI)can be attributed to three mutually uncoupled physical mechanisms,i.e.,the generation of interface traps(ΔV_(IT)),hole trapping in pre-existing gate oxide defects(ΔV_(HT)),and the generation of gate oxide defects(ΔV_(OT)).In this work,the characteristic of NBTI for p-type MOSFET fabricated by using a 28-nm high-k metal gate(HKMG)process is thoroughly studied.The experimental results show that the degradation is enhanced at a larger stress bias and higher temperature.The effects of the three underlying subcomponents are evaluated by using the comprehensive models.It is found that the generation of interface traps dominates the NBTI degradation during long-time NBTI stress.Moreover,the NBTI parameters of the power-law time exponent and temperature activation energy as well as the gate oxide field acceleration are extracted.The dependence of operating lifetime on stress bias and temperature is also discussed.It is observed that NBTI lifetime significantly decreases as the stress increases.Furthermore,the decrease of charges related to interface traps and hole detrapping in pre-existing gate oxide defects are used to explain the recovery mechanism after stress.展开更多
文摘The impacts of shallow trench isolation(STI)indium implantation on gate oxide and device characteristics are studied in this work.The stress modulation effect is confirmed in this research work.An enhanced gate oxide oxidation rate is observed due to the enhanced tensile stress,and the thickness gap is around 5%.Wafers with and without STI indium implantation are manufactured using the 150-nm silicon on insulator(SOI)process.The ramped voltage stress and time to breakdown capability of the gate oxide are researched.No early failure is observed for both wafers the first time the voltage is ramped up.However,a time dependent dielectric breakdown(TDDB)test shows more obvious evidence that the gate oxide quality is weakened by the STI indium implantation.Meanwhile,the device characteristics are compared,and the difference between two devices is consistent with the equivalent oxide thickness(EOT)gap.
基金the National Natural Science Foundation of China (Grant Nos. 61774052 and 61904045)the National Research and Development Program for Major Research Instruments of China (Grant No. 62027814)the Natural Science Foundation of Jiangxi Province, China (Grant No. 20212BAB214047)。
文摘A split-gate SiC trench gate MOSFET with stepped thick oxide, source-connected split-gate(SG), and p-type pillar(ppillar) surrounded thick oxide shielding region(GSDP-TMOS) is investigated by Silvaco TCAD simulations. The sourceconnected SG region and p-pillar shielding region are introduced to form an effective two-level shielding, which reduces the specific gate–drain charge(Q_(gd,sp)) and the saturation current, thus reducing the switching loss and increasing the short-circuit capability. The thick oxide that surrounds a p-pillar shielding region efficiently protects gate oxide from being damaged by peaked electric field, thereby increasing the breakdown voltage(BV). Additionally, because of the high concentration in the n-type drift region, the electrons diffuse rapidly and the specific on-resistance(Ron,sp) becomes smaller.In the end, comparing with the bottom p~+ shielded trench MOSFET(GP-TMOS), the Baliga figure of merit(BFOM,BV~2/R_(on,sp)) is increased by 169.6%, and the high-frequency figure of merit(HF-FOM, R_(on,sp) × Q_(gd,sp)) is improved by310%, respectively.
文摘Degradation induced by the negative bias temperature instability(NBTI)can be attributed to three mutually uncoupled physical mechanisms,i.e.,the generation of interface traps(ΔV_(IT)),hole trapping in pre-existing gate oxide defects(ΔV_(HT)),and the generation of gate oxide defects(ΔV_(OT)).In this work,the characteristic of NBTI for p-type MOSFET fabricated by using a 28-nm high-k metal gate(HKMG)process is thoroughly studied.The experimental results show that the degradation is enhanced at a larger stress bias and higher temperature.The effects of the three underlying subcomponents are evaluated by using the comprehensive models.It is found that the generation of interface traps dominates the NBTI degradation during long-time NBTI stress.Moreover,the NBTI parameters of the power-law time exponent and temperature activation energy as well as the gate oxide field acceleration are extracted.The dependence of operating lifetime on stress bias and temperature is also discussed.It is observed that NBTI lifetime significantly decreases as the stress increases.Furthermore,the decrease of charges related to interface traps and hole detrapping in pre-existing gate oxide defects are used to explain the recovery mechanism after stress.