Parasitic capacitances associated with overhangs of the T-shape-gate enhancement-mode(E-mode)GaN-based power device,were investigated by frequency/voltage-dependent capacitance-voltage and inductive-load switching mea...Parasitic capacitances associated with overhangs of the T-shape-gate enhancement-mode(E-mode)GaN-based power device,were investigated by frequency/voltage-dependent capacitance-voltage and inductive-load switching measurements.The overhang capacitances induce a pinch-off voltage distinguished from that of the E-mode channel capacitance in the gate capacitance and the gatedrain capacitance characteristic curves.Frequency-and voltage-dependent tests confirm the instability caused by the trapping of interface/bulk states in the LPCVD-SiNx passivation dielectric.Circuit-level double pulse measurement also reveals its impact on switching transition for power switching applications.展开更多
A systemic and comprehensive ESD-induced parasitic model is presented in this paper, which is used to analyse the parasitic influences of electrostatic discharge （ESD） protection circuits on the performance of radio...A systemic and comprehensive ESD-induced parasitic model is presented in this paper, which is used to analyse the parasitic influences of electrostatic discharge （ESD） protection circuits on the performance of radio frequency applications. A novel low-parasitic ESD protection structure is made in a 0.35μm 1P3M silicide CMOS process. The measured results show that this novel structure has a low parasitic capacitance about 310fF and a low leakage current about 12.2nA with a suitable ESD robustness target about 5kV human body model.展开更多
The conformal mapping of an electric field has been employed to develop an accurate parasitic capacitance model for nanoscale fin field-effect transistor（Fin FET） device. Firstly, the structure of the dual-layer spa...The conformal mapping of an electric field has been employed to develop an accurate parasitic capacitance model for nanoscale fin field-effect transistor（Fin FET） device. Firstly, the structure of the dual-layer spacers and the gate parasitic capacitors are thoroughly analyzed. Then, the Cartesian coordinate is transferred into the elliptic coordinate and the equivalent fringe capacitance model can be built-up by some arithmetical operations. In order to validate our proposed model, the comparison of statistical analysis between the proposed calculation and the 3D-TCAD simulation has been carried out, and several different material combinations of the dual-k structure have been considered. The results show that the proposed analytical model can accurately calculate the fringe capacitance of the Fin FET device with dual-k spacers.展开更多
The effects of parasitic capacitance in induction motor system are unnoticed when it is fed from the AC line, but they are obvious when supplied directly from a PWM inverter. Consequently, many parasitic problems occu...The effects of parasitic capacitance in induction motor system are unnoticed when it is fed from the AC line, but they are obvious when supplied directly from a PWM inverter. Consequently, many parasitic problems occur, such as motor to earth leakage current, bearing current, incoming line current distortion and uneven distribution of electrical stresses along the winding. On the basis of the uniform transmission line principle, a complete equivalent circuit of the PWM inverter fed motor system is presented, based on which all the capacitive parasitic problems mentioned above are analyzed and simulated by means of PSPICE. All the results are consistent with the existing ones.展开更多
In this paper,ground-signal-ground type through-silicon vias（TSVs） exploiting air gaps as insulation layers are designed,analyzed and simulated for applications in millimeter wave.The compact wideband equivalent-cir...In this paper,ground-signal-ground type through-silicon vias（TSVs） exploiting air gaps as insulation layers are designed,analyzed and simulated for applications in millimeter wave.The compact wideband equivalent-circuit model and passive elements（RLGC） parameters based on the physical parameters are presented with the frequency up to 100 GHz.The parasitic capacitance of TSVs can be approximated as the dielectric capacitance of air gaps when the thickness of air gaps is greater than 0.75 μm.Therefore,the applied voltage of TSVs only needs to achieve the flatband voltage,and there is no need to indicate the threshold voltage.This is due to the small permittivity of air gaps.The proposed model shows good agreement with the simulation results of ADS and Ansoft＇s HFSS over a wide frequency range.展开更多
在评估和优化半导体器件开关瞬态特性领域,解析模型因具有简单、直观、应用便捷等优点得到广泛研究。相较同等功率等级的硅基功率器件,碳化硅(silicon carbide,SiC)金属氧化物半导体场效应晶体管(metal-oxide-semiconductor field effec...在评估和优化半导体器件开关瞬态特性领域,解析模型因具有简单、直观、应用便捷等优点得到广泛研究。相较同等功率等级的硅基功率器件,碳化硅(silicon carbide,SiC)金属氧化物半导体场效应晶体管(metal-oxide-semiconductor field effect transistor,MOSFET)可以应用于更高开关速度,其开关瞬态特性更为复杂,开关瞬态解析建模也更加困难。该文总结现有的针对SiC MOSFET与二极管换流对的开关瞬态解析建模方法,在建模过程中依次引入各种简化假设,按照简化程度由低到高的顺序,梳理解析建模的逐步简化过程。通过对比,评估各模型的优缺点以及适用场合,对其中准确性、实用性都较强的分段线性模型进行详细介绍;之后,对开关瞬态建模中关键参数的建模方法进行总结与评价;最后,指出现有SiC MOSFET开关瞬态解析模型中存在的问题,并对其未来发展给出建议。展开更多
基金the National Natural Science Foundation of China under Grant 61822407,Grant 61527816,Grant 11634002,Grant 61631021,Grant 62074161,Grant 62004213,and Grant U20A20208in part by the Key Research Program of Frontier Sciences,Chinese Academy of Sciences(CAS)under Grant QYZDB-SSW-JSC012+2 种基金in part by the Youth Innovation Promotion Association of CASin part by the University of CASthe Opening Project of Key Laboratory of Microelectronic Devices&Integrated Technology,Institute of Microelectronics,CAS.
文摘Parasitic capacitances associated with overhangs of the T-shape-gate enhancement-mode(E-mode)GaN-based power device,were investigated by frequency/voltage-dependent capacitance-voltage and inductive-load switching measurements.The overhang capacitances induce a pinch-off voltage distinguished from that of the E-mode channel capacitance in the gate capacitance and the gatedrain capacitance characteristic curves.Frequency-and voltage-dependent tests confirm the instability caused by the trapping of interface/bulk states in the LPCVD-SiNx passivation dielectric.Circuit-level double pulse measurement also reveals its impact on switching transition for power switching applications.
文摘A systemic and comprehensive ESD-induced parasitic model is presented in this paper, which is used to analyse the parasitic influences of electrostatic discharge （ESD） protection circuits on the performance of radio frequency applications. A novel low-parasitic ESD protection structure is made in a 0.35μm 1P3M silicide CMOS process. The measured results show that this novel structure has a low parasitic capacitance about 310fF and a low leakage current about 12.2nA with a suitable ESD robustness target about 5kV human body model.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61574056 and 61204038)the Natural Science Foundation of Shanghai,China(Grant No.14ZR1412000)
文摘The conformal mapping of an electric field has been employed to develop an accurate parasitic capacitance model for nanoscale fin field-effect transistor（Fin FET） device. Firstly, the structure of the dual-layer spacers and the gate parasitic capacitors are thoroughly analyzed. Then, the Cartesian coordinate is transferred into the elliptic coordinate and the equivalent fringe capacitance model can be built-up by some arithmetical operations. In order to validate our proposed model, the comparison of statistical analysis between the proposed calculation and the 3D-TCAD simulation has been carried out, and several different material combinations of the dual-k structure have been considered. The results show that the proposed analytical model can accurately calculate the fringe capacitance of the Fin FET device with dual-k spacers.
文摘The effects of parasitic capacitance in induction motor system are unnoticed when it is fed from the AC line, but they are obvious when supplied directly from a PWM inverter. Consequently, many parasitic problems occur, such as motor to earth leakage current, bearing current, incoming line current distortion and uneven distribution of electrical stresses along the winding. On the basis of the uniform transmission line principle, a complete equivalent circuit of the PWM inverter fed motor system is presented, based on which all the capacitive parasitic problems mentioned above are analyzed and simulated by means of PSPICE. All the results are consistent with the existing ones.
基金Project supported by the National Basic Research Program of China(Grant No.2014CB339900)the National Natural Science Foundation of China(Grant Nos.61376039,61334003,61574104,and 61474088)
文摘In this paper,ground-signal-ground type through-silicon vias（TSVs） exploiting air gaps as insulation layers are designed,analyzed and simulated for applications in millimeter wave.The compact wideband equivalent-circuit model and passive elements（RLGC） parameters based on the physical parameters are presented with the frequency up to 100 GHz.The parasitic capacitance of TSVs can be approximated as the dielectric capacitance of air gaps when the thickness of air gaps is greater than 0.75 μm.Therefore,the applied voltage of TSVs only needs to achieve the flatband voltage,and there is no need to indicate the threshold voltage.This is due to the small permittivity of air gaps.The proposed model shows good agreement with the simulation results of ADS and Ansoft＇s HFSS over a wide frequency range.
