Flexible planar micro supercapacitor diode

Supercapacitor diode is a novel ion device that performs both supercapacitor energy storage and ion diode rectification functions.However,previously reported devices are limited by their large size and complex processes.In this work,we demonstrate a screen-printed micro supercapacitor diode(MCAPode)that based on the insertion of a finger mode with spinel ZnCo_(2)O_(4) as cathode and activated carbon as anode for the first time,and featuring an excellent area specific capacitance(1.21 mF cm^(-2)at 10 mV s^(-1))and high rectification characteristics(rectification ratioⅠof 11.99 at 40 mV s^(-1)).Taking advantage of the ionic gel electrolyte,which provides excellent stability during repeated flexing and at high temperatures.In addition,MCAPode exhibits excellent electrochemical performance and rectification capability in"AND"and"OR"logic gates.These findings provide practical solutions for future expansion of micro supercapacitor diode applications.

A SiC asymmetric cell trench MOSFET with a split gate and integrated p^(+)-poly Si/SiC heterojunction freewheeling diode

A new SiC asymmetric cell trench metal–oxide–semiconductor field effect transistor(MOSFET)with a split gate(SG)and integrated p^(+)-poly Si/SiC heterojunction freewheeling diode(SGHJD-TMOS)is investigated in this article.The SG structure of the SGHJD-TMOS structure can effectively reduce the gate-drain capacitance and reduce the high gateoxide electric field.The integrated p^(+)-poly Si/SiC heterojunction freewheeling diode substantially improves body diode characteristics and reduces switching losses without degrading the static characteristics of the device.Numerical analysis results show that,compared with the conventional asymmetric cell trench MOSFET(CA-TMOS),the high-frequency figure of merit(HF-FOM,R_(on,sp)×Q_(gd,sp))is reduced by 92.5%,and the gate-oxide electric field is reduced by 75%.In addition,the forward conduction voltage drop(V_(F))and gate-drain charge(Q_(gd))are reduced from 2.90 V and 63.5μC/cm^(2) in the CA-TMOS to 1.80 V and 26.1μC/cm^(2) in the SGHJD-TMOS,respectively.Compared with the CA-TMOS,the turn-on loss(E_(on)) and turn-off loss(E_(off)) of the SGHJD-TMOS are reduced by 21.1%and 12.2%,respectively.

FORWARD GATED-DIODE R-G CURRENT METHOD: A SIMPLE NOVEL TECHNIQUE FOR CHARACTERIZING LATERAL LIGHTLY DOPING REGION OF LDD MOSFET's

This paper presents a simple novel technique-forward gated-diode R-G current method-to determine the lateral lightly-doped source/drain (S/D) region interface state density and effective surface doping concentration of the lightly-doped drain (LDD) N- MOSFET's simultaneously. One interesting result of the numerical analysis is the direct characterization of the interface state density and characteristic gate voltage values corresponding to LDD effective surface doping concentration. It is observed that the S/D N- surface doping concentration and corresponding region's interface state density are R-G current peak position and amplitude dependent, respectively. It is convincible that the proposed method is well suitable for the characterization of deep sub-micron MOSFET's in the current ULSI technology.

A novel diode string triggered gated-Pi N junction device for electrostatic discharge protection in 65-nm CMOS technology

A novel diode string-triggered gated-Pi N junction device, which is fabricated in a standard 65-nm complementary metal-oxide semiconductor（CMOS） technology, is proposed in this paper. An embedded gated-Pi N junction structure is employed to reduce the diode string leakage current to 13 n A/μm in a temperature range from 25°C to 85°C. To provide the effective electrostatic discharge（ESD） protection in multi-voltage power supply, the triggering voltage of the novel device can be adjusted through redistributing parasitic resistance instead of changing the stacked diode number.

FORWARD GATED-DIODE METHOD FOR DIRECTLY MEASURING STRESS-INDUCED INTERFACE TRAPS IN NMOSFET/SOI

Forward gated-diode Recombination-Generation(R-G) current method is applied to an NMOSFET/SOI to measure the stress-induced interface traps in this letter. This easy but accurate experimental method can directly give stress-induced average interface traps for characterizing the device's hot carrier characteristics. For the tested device, an expected power law relationship of ANit ～ t0.787 between pure stress-induced interface traps and accumulated stressing time is obtained.

FORWARD GATED-DIODE METHOD FOR EXTRACTING HOT-CARRIER-STRESS-INDUCED BACK INTERFACE TRAPS IN SOI/NMOSFETs

The forward gated-diode R-G current method for extracting the hot-carrier-stress-induced back interface traps in SOI/NMOSFET devices has been demonstrated in this letter. This easy and accurate experimental method directly gives the induced interface trap density from the measured R-G current peak of the gated-diode architecture. An expected power law relationship between the induced back interface trap density and the accumulated stress time has been obtained.

Research on high-voltage 4H-SiC P-i-N diode with planar edge junction termination techniques

The planar edge termination techniques of junction termination extension （JTE） and offset field plates and fieldlimiting rings for the 4H-SiC P i-N diode were investigated and optimized by using a two-dimensional device simulator ISE-TCAD10.0. By experimental verification, a good consistency between simulation and experiment can be observed. The results show that the reverse breakdown voltage for the 4H-SiC P-i-N diode with optimized JTE edge termination can accomplish near ideal breakdown voltage and much lower leakage current. The breakdown voltage can be near 1650 V, which achieves more than 90 percent of ideal parallel plane junction breakdown voltage and the leakage current density can be near 3 ×10^-5 A/cm2.

High performance trench MOS barrier Schottky diode with high-k gate oxide

A novel trench MOS barrier Schottky diode（TMBS） device with a high-k material introduced into the gate insulator is reported, which is named high-k TMBS. By simulation with Medici, it is found that the high-k TMBS can have 19.8% lower leakage current while maintaining the same breakdown voltage and forward turn-on voltage compared with the conventional regular trench TMBS.

A 4H-SiC merged P–I–N Schottky with floating back-to-back diode

A novel 4 H-Si C merged P–I–N Schottky(MPS)with floating back-to-back diode(FBD),named FBD-MPS,is proposed and investigated by the Sentaurus technology computer-aided design(TCAD)and analytical model.The FBD features a trench oxide and floating P-shield,which is inserted between the P+/N-(PN)junction and Schottky junction to eliminate the shorted anode effect.The FBD is formed by the N-drift/P-shield/N-drift and it separates the PN and Schottky active region independently.The FBD reduces not only the Vturn to suppress the snapback effect but also the Von at bipolar operation.The results show that the snapback can be completely eliminated,and the maximum electric field(Emax)is shifted from the Schottky junction to the FBD in the breakdown state.

High contrast all-optical diode based on direction-dependent optical bistability within asymmetric ring cavity

We propose a simple all-optical diode which is comprised of an asymmetric ring cavity containing a two-level atomic ensemble. Attributed to spatial symmetry breaking of the ring cavity, direction-dependent optical bistability is obtained in a classical bistable system. Therefore, a giant optical non-reciprocity is generated, which guarantees an all-optical diode with a high contrast up to 22 d B. Furthermore, its application as an all-optical logic AND gate is also discussed.

Numerical analysis of In_(0.53) Ga_(0.47) As/InP single photon avalanche diodes

A rigorous theoretical model for Ino.53Gao.47As/InP single photon avalanche diode is utilized to investigate the dependences of single photon quantum efficiency and dark count probability on structure and operation condition. In the model, low field impact ionizations in charge and absorption layers are allowed, while avalanche breakdown can occur only in the multiplication layer. The origin of dark counts is discussed and the results indicate that the dominant mechanism that gives rise to dark counts depends on both device structure and operating condition. When the multiplication layer is thicker than a critical thickness or the temperature is higher than a critical value, generation-recombination in the absorption layer is the dominative mechanism; otherwise band-to-band tunneling in the multiplication layer dominates the dark counts. The thicknesses of charge and multiplication layers greatly affect the dark count and the peak single photon quantum efficiency and increasing the multiplication layer width may reduce the dark count probability and increase the peak single photon quantum efficiency. However, when the multiplication layer width exceeds 1 μm, the peak single photon quantum efficiency increases slowly and it is finally saturated at the quantum efficiency of the single photon avalanche diodes.

3300 V高性能混合SiC模块研制

将Si基绝缘栅双极型晶体管(Insulated gate bipolar transistor,IGBT)芯片与SiC结型势垒肖特基二极管芯片按照双开关电路结构排布,开发了一种3 300 V等级混合SiC模块,对其设计方法、封装工艺、仿真、测试结果进行分析,并对标相同规格IGBT模块。混合SiC模块低空洞率焊接满足牵引领域高温度循环周次的要求,冗余式的连跳键合结构可以有效增强功率循环能力。采用双脉冲法测试动态性能,测试结果表明该混合SiC模块反向恢复时间减小了84%,反向恢复电流减小了89.5%,反向恢复能量减小了99%,一次开关产生的总损耗降低了43.3%。混合SiC模块消除了开关过程中电压和电流过冲现象,在高电压、大电流和高频率的应用工况下具有明显的优势。

Effects of back gate bias on radio-frequency performance in partially depleted silicon-on-inslator nMOSFETs

The effects of back gate bias(BGEs) on radio-frequency(RF) performances in PD SOI n MOSFETs are presented in this paper. Floating body(FB) device, T-gate body-contact(TB) device, and tunnel diode body-contact(TDBC) device, of which the supply voltages are all 1.2 V, are compared under different back gate biases by different figures of merit, such as cut-off frequency( fT), maximum frequency of oscillation( fmax), etc. Because of the lack of a back gate conducting channel, the drain conductance(gd) of TDBC transistor shows a smaller degradation than those of the others, and the trans-conductance(gm) of TDBC is almost independent of back gate bias. The values of fT of TDBC are also kept nearly constant under different back gate biases. However, RF performances of FB and TB each show a significant degradation when the back gate bias is larger than ～ 20 V. The results indicate that TDBC structures could effectively improve the back gate bias in RF performance.

Forward gated-diode method for parameter extraction of MOSFETs

The forward gated-diode method is used to extract the dielectric oxide thickness and body doping concentration of MOSFETs, especially when both of the variables are unknown previously. First, the dielectric oxide thickness and the body doping concentration as a function of forward gated-diode peak recombination-generation （R-G） current are derived from the device physics. Then the peak R-G current characteristics of the MOSFETs with different dielectric oxide thicknesses and body doping concentrations are simulated with ISE-Dessis for parameter extraction. The results from the simulation data demonstrate excellent agreement with those extracted from the forward gated-diode method.

Clear correspondence between gated-diode R-G current and performance degradation of SOI n-MOSFETs after F-N stress tests

A clear correspondence between the gated-diode generation-recombination （R-G） current and the performance degradation of an SOI n-channel MOS transistor after F-N stress tests has been demonstrated. Due to the increase of interface traps after F-N stress tests, the R-G current of the gated-diode in the SOI-MOSFET architecture increases while the performance characteristics of the MOSFET transistor such as the saturation drain current and sub-threshold slope are degraded. From a series of experimental measurements of the gated-diode and SOI-MOSFET DC characteristics, a linear decrease of the drain saturation current and increase of the threshold voltage as well as a like-line rise of the sub-threshold swing and a corresponding degradation in the trans-conductance are also observed. These results provide theoretical and experimental evidence for us to use the gated-diode tool to monitor SOI-MOSFET degradation.

Double-gate tunnel field-effect transistor:Gate threshold voltage modeling and extraction

The tunnel field-effect transistor(TFET) is a potential candidate for the post-CMOS era.As one of the most important electrical parameters of a device,double gate TFET(DG-TFET) gate threshold voltage was studied.First,a numerical simulation study of transfer characteristic and gate threshold voltage in DG-TFET was reported.Then,a simple analytical model for DG-TFET gate threshold voltage VTG was built by solving quasi-two-dimensional Poisson equation in Si film.The model as a function of the drain voltage,the Si layer thickness,the gate length and the gate dielectric was discussed.It is shown that the proposed model is consistent with the simulation results.This model should be useful for further investigation of performance of circuits containing TFETs.

GaN HEMT及GaN栅驱动电路在DToF激光雷达中的应用

DToF(Direct Time-of-Flight)激光雷达通过直接测量激光的飞行时间完成距离测量和地图成像,应用于自动驾驶的DToF激光雷达需要具备更高的分辨率和更宽的检测范围。GaN高电子迁移率晶体管(HEMT)相对于传统Si基功率MOSFET的优异特性使其非常适合应用于自动驾驶中的DToF激光雷达,而GaN HEMT性能的发挥依赖于高速、高驱动能力和高可靠性的GaN栅驱动电路。针对应用于自动驾驶的DToF激光雷达系统,从系统电路到核心元器件,分析了激光二极管驱动电路面临的设计挑战、GaN HEMT的优势以及GaN栅驱动电路面临的设计挑战,并介绍了适合该应用的GaN栅驱动电路。

距离选通成像系统中短脉冲激光驱动技术研究

基于单光子探测的距离选通成像系统中,需发射短脉冲激光并进行发射器和接收器之间的同步控制,使探测器工作在光子计数模式并在时间上进行积分,以完成成像操作。为了获得满足系统要求的短脉冲激光,同时减小系统体积、降低系统成本,本文提出将基于射频双极晶体管和基于阶跃恢复二极管SRD(结合短路传输线)两种产生窄脉冲电路应用于单光子距离选通成像系统。介绍了二者的原理与设计方法,进行了仿真验证、实物制作及测试,对脉冲发生器的特点、影响脉宽幅值的因素进行了分析。实物测试结果表明,基于晶体管方式可以产生上升时间为903.5 ps、下降时间为946.1 ps、脉冲宽度为824 ps、幅度为2.46 V的窄脉冲。基于SRD方式可以产生上升时间为456.8 ps、下降时间为458.3 ps、脉冲宽度为1.5 ns、幅度为2.38 V的窄脉冲,二者重复频率皆可达到50 MHz。利用这两种设计方法的任何一种配合外部电流驱动激光二极管都能够获得性能优良的短脉冲激光输出。

Fin Field Effect Transistor with Active 4-Bit Arithmetic Operations in 22 nm Technology

A design of a high-speed multi-core processor with compact size is a trending approach in the Integrated Circuits(ICs)fabrication industries.Because whenever device size comes down into narrow,designers facing many power den-sity issues should be reduced by scaling threshold voltage and supply voltage.Initially,Complementary Metal Oxide Semiconductor(CMOS)technology sup-ports power saving up to 32 nm gate length,but further scaling causes short severe channel effects such as threshold voltage swing,mobility degradation,and more leakage power(less than 32)at gate length.Hence,it directly affects the arithmetic logic unit(ALU),which suffers a significant power density of the scaled multi-core architecture.Therefore,it losses reliability features to get overheating and increased temperature.This paper presents a novel power mini-mization technique for active 4-bit ALU operations using Fin Field Effect Tran-sistor(FinFET)at 22 nm technology.Based on this,a diode is directly connected to the load transistor,and it is active only at the saturation region as a function.Thereby,the access transistor can cutoff of the leakage current,and sleep transis-tors control theflow of leakage current corresponding to each instant ALU opera-tion.The combination of transistors(access and sleep)reduces the leakage current from micro to nano-ampere.Further,the power minimization is achieved by con-necting the number of transistors(6T and 10T)of the FinFET structure to ALU with 22 nm technology.For simulation concerns,a Tanner(T-Spice)with 22 nm technology implements the proposed design,which reduces threshold vol-tage swing,supply power,leakage current,gate length delay,etc.As a result,it is quite suitable for the ALU architecture of a high-speed multi-core processor.

Implementation of an All-Optical NOR Gate Using a Multi-Wavelength Injection-Locked Diode Laser

We demonstrated an all optical NOR gate operating at 10 Gb/s using a multi-wavelength mutual injection-locked Fabry-Perot laser diode (FP-LD).