Modeling of Gate Tunneling Current for Nanoscale MOSFETs with High-k Gate Stacks

A quantum model based on solutions to the Schrodinger-Poisson equations is developed to investigate the device behavior related togate tunneling current for nanoscale MOSFETs with high-k gate stacks. This model can model various MOS device structures with combinations of high-k dielectric materials and multilayer gate stacks,revealing quantum effects on the device performance. Comparisons are made for gate current behavior between nMOSFET and pMOSFET high- k gate stack structures. The results presented are consistent with experimental data, whereas a new finding for an optimum nitrogen content in HfSiON gate dielectric requires further experimental verifications.

Gate Current for MOSFETs with High k Dielectric Materials

The MOSFET gate currents of high k gate dielectrics due to direct tunneling are investigated by using a new direct tunneling current model developed.The model includes both the inversion layer quantization effect with finite barrier height and the polysilicon depletion effect.The impacts of dielectric constant and conduction band offset as well as the band gap on the gate current are discussed.The results indicate that the gate dielectric materials with higher dielectric constant,larger conduction band offset and the larger band gap are necessary to reduce the gate current.The calculated results can be used as a guide to select the appropriate high k gate dielectric materials for MOSFETs.

Modified model of gate leakage currents in AlGaN/GaN HEMTs

It has been reported that the gate leakage currents are described by the Frenkel-Poole emission(FPE) model,at temperatures higher than 250 K.However,the gate leakage currents of our passivated devices do not accord with the FPE model.Therefore,a modified FPE model is developed in which an additional leakage current,besides the gate(ⅠⅡ),is added.Based on the samples with different passivations,the ⅠⅡcaused by a large number of surface traps is separated from total gate currents,and is found to be linear with respect to(φB-Vg)0.5.Compared with these from the FPE model,the calculated results from the modified model agree well with the Ig-Vgmeasurements at temperatures ranging from 295 K to 475 K.

Effect of SiN:H_x passivation layer on the reverse gate leakage current in GaN HEMTs

This paper concentrates on the impact of SiN passivation layer deposited by plasma-enhanced chemical vapor deposition（PECVD） on the Schottky characteristics in GaN high electron mobility transistors（HEMTs）. Three types of SiN layers with different deposition conditions were deposited on GaN HEMTs. Atomic force microscope（AFM）, capacitance-voltage（C-V）, and Fourier transform infrared（FTIR） measurement were used to analyze the surface morphology, the electrical characterization, and the chemical bonding of SiN thin films, respectively. The better surface morphology was achieved from the device with lower gate leakage current. The fixed positive charge Qf was extracted from C-V curves of Al/SiN/Si structures and quite different density of trap states（in the order of magnitude of 1011-1012 cm^（-2）） was observed.It was found that the least trap states were in accordance with the lowest gate leakage current. Furthermore, the chemical bonds and the %H in Si-H and N-H were figured from FTIR measurement, demonstrating an increase in the density of Qf with the increasing %H in N-H. It reveals that the effect of SiN passivation can be improved in GaN-based HEMTs by modulating %H in Si-H and N-H, thus achieving a better Schottky characteristics.

The leakage current mechanisms in the Schottky diode with a thin Al layer insertion between Al_(0.245)Ga_(0.755)N/GaN heterostructure and Ni/Au Schottky contact

This paper investigates the behaviour of the reverse-bias leakage current of the Schottky diode with a thin Al inserting layer inserted between Al0.245Ga0.755N/GaN heterostructure and Ni/Au Schottky contact in the temperature range of 25 350℃. It compares with the Schottky diode without Aluminium inserting layer. The experimental results show that in the Schottky diode with Al layer the minimum point of I-V curve drifts to the minus voltage, and with the increase of temperature increasing, the minimum point of I V curve returns the 0 point. The temperature dependence of gate-leakage currents in the novelty diode and the traditional diode are studied. The results show that the Al inserting layer introduces interface states between metal and Al0.245Ga0.755N. Aluminium reacted with oxygen formed Al2O3 insulator layer which suppresses the trap tunnelling current and the trend of thermionic field emission current. The reliability of the diode at the high temperature is improved by inserting a thin Al layer.

The electrical characteristics of a 4H-silicon carbide metal-insulator-semiconductor structure with Al_2O_3 as the gate dielectric

A 4H-silicon carbide metal-insulator-semiconductor structure with ultra-thin Al2O3 as the gate dielectric, deposited by atomic layer deposition on tile epitaxial layer of a 4H-SiC （0001） 80N-/N＋ substrate, has been fabricated. The experimental results indicate that the prepared ultra-thin Al2O3 gate dielectric exhibits good physical and electrical characteristics, including a high breakdown electrical field of 25 MV/cm, excellent interface properties （1 × 10^14 cm^-2） and low gate-leakage current （IG = 1 × 10^-3 A/cm 2@Eox = 8 MV/cm）. Analysis of the current conduction mecha- nism on the deposited Al2O3 gate dielectric was also systematically performed. The confirmed conduction mechanisms consisted of Fowler-Nordheim （FN） tuaneling, the Frenkel-Poole mechanism, direct tunneling and Schottky emission, and the dominant current conduction mechanism depends on the applied electrical field. When the gate leakage current mechanism is dominated by FN tunneling, the barrier height of SiC/Al2O3 is 1.4 eV, which can meet the requirements of silicon carbide metal-insulator-semiconductor transistor devices.

Performance comparison of Pt/Au and Ni/Au Schottky contacts on Al_xGa_(1-x)N/GaN heterostructures at high temperatures

In contrast with Au/Ni/Al0.25Ga0.75N/GaN Schottky contacts, this paper systematically investigates the effect of thermal annealing of Au/Pt/Alo.25Ga0.75N/GaN structures on electrical properties of the two-dimensional electron gas in Alo.25Ga0.75N/CaN heterostructures by means of temperature-dependent Hall and temperature-dependent current-voltage measurements. The two-dimensional electron gas density of the samples with Pt cap layer increases after annealing in N2 ambience at 600℃ while the annealing treatment has little effect on the two-dimensional electron gas mobility in comparison with the samples with Ni cap layer. The experimental results indicate that the Au/Pt/Al0.25Ga0.75N/GaN Schottky contacts reduce the reverse leakage current density at high annealing temperatures of 400-600 ℃. As a conclusion, the better thermal stability of the Au/Pt/Alo.25Gao.75N/GaN Schottky contacts than the Au/Ni/Al0.25Ga0.75N/GaN Schottky contacts at high temperatures can be attributed to the inertness of the interface between Pt and AlxGa1-xN.

Theoretical study of the SiO_2/Si interface and its effect on energy band profile and MOSFET gate tunneling current

Two SiO_2/Si interface structures,which are described by the double bonded model（DBM） and the bridge oxygen model（BOM）,have been theoretically studied via first-principle calculations.First-principle simulations demonstrate that the width of the transition region for the interface structure described by DBM is larger than that for the interface structure described by BOM.Such a difference will result in a difference in the gate leakage current. Tunneling current calculation demonstrates that the SiO_2/Si interface structure described by DBM leads to a larger gate leakage current.

Analytical modeling of the direct tunneling current through high-k gate stacks for long-channel cylindrical surrounding-gate MOSFETs

An analytical direct tunneling gate current model for cylindrical surrounding gate（CSG） MOSFETs with high-k gate stacks is developed. It is found that the direct tunneling gate current is a strong function of the gate＇s oxide thickness, but that it is less affected by the change in channel radius. It is also revealed that when the thickness of the equivalent oxide is constant, the thinner the first layer, the smaller the direct tunneling gate current.Moreover, it can be seen that the dielectric with a higher dielectric constant shows a lower tunneling current than expected. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE.

Gate current modeling and optimal design of nanoscale non-overlapped gate to source/drain MOSFET

A novel nanoscale MOSFET with a source/drain-to-gate non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time.The gate leakage behaviour of the novel MOSFET structure has been investigated with the help of a compact analytical model and Sentaurus simulation. A fringing gate electric field through the dielectric spacer induces an inversion layer in the non-overlap region to act as an extended S/D（source/drain） region.It is found that an optimal source/drain-to-gate non-overlapped and high-A：spacer structure has reduced the gate leakage current to a great extent as compared to those of an overlapped structure.Further,the proposed structure had improved off current,subthreshold slope and drain induced barrier lowering（DIBL） characteristics.It is concluded that this structure solves the problem of high leakage current without introducing extra series resistance.

The passivation mechanism of nitrogen ions on the gate leakage current of HfO_2/AlGaN/GaN MOS-HEMTs

In this paper, we systematically study the positive gate leakage current in AlGaN/GaN metal-oxide-semiconductor high electron-mobility transistors (MOS-HEMTs) with HfO 2 dielectric using atomic layer deposition (ALD). We observe that the incorporated nitrogen ions will improve the positive gate leakage current of devices obviously, but do not change the reverse gate leakage current. The passivation mechanism of nitrogen ions in oxygen vacancies in HfO 2 is studied by first-principles calculations. It is shown that the gap states of HfO 2 caused by oxygen vacancies increase the positive gate leakage current of MOS-HEMTs. Nitrogen ions passivate the gap states of HfO 2 and decrease the positive gate leakage current but do not effect the reverse gate leakage current.

Modeling of current–voltage characteristics for dual-gate amorphous silicon thin-film transistors considering deep Gaussian density-of-state distribution

Accounting for the deep Gaussian and tail exponential distribution of the density of states, a physical approximation for potentials of amorphous silicon thin-film transistors using a symmetric dual gate （sDG a-Si：H TFT） has been presented. The proposed scheme provides a complete solution of the potentials at the surface and center of the layer without solving any transcendental equations. A channel current model incorporating features of gate voltage-dependent mobility and coupling factor is derived. We show the parameters required for accurately describing the current-voltage （l-V） characteristics of DG a-Si：H TFT and just how sensitively these parameters affect TFT current. Particularly, the parameters＇ dependence on the I-V characteristics with respect to the density of deep state and channel thickness has been investigated in detail. The resulting scheme and model are successively verified through comparison with numerical simulations as well as the available experimental data.

Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO_2/high-k gate stacked dielectric

A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of great importance. In this paper we have explored the gate tunneling current of a double gate junctionless transistor（DGJLT） for the first time through an analytical model, to meet the future requirement of expected high-k gate dielectric material that could replace SiO2. We therefore present the high-k gate stacked architecture of the DGJLT to minimize the gate tunneling current. This paper also demonstrates the impact of conduction band offset,workfunction difference and k-values on the tunneling current of the DGJLT.

Effective interface passivation of a Ge/HfO_2 gate stack using ozone pre-gate treatment and ozone ambient annealing

The physical and electrical properties of a Ge/GeO2/HfO2/Al gate stack are investigated.A thin interfacial GeO2 layer（- 1 nm） is formed between Ge and HfO2 by dual ozone treatments,which passivates the Ge/high-k interface.Capacitors on p-type Ge substrates show very promising capacitance-voltage（C-V） characteristics by using in situ pre-gate ozone passivation and ozone ambient annealing after high-k deposition,indicating efficient passivation of the Ge/HfO2 interface.It is shown that the mid-gap interface state density at the Ge/GeO2 interface is 6.4×10^11 cm^-2·eV^-1.In addition,the gate leakage current density of the Ge/GeO2/HfO2/Al gate stack passivated by the dual ozone treatments is reduced by about three orders of magnitude compared to that of a Ge/HfO2/Al gate stack without interface passivation.

Preparation of a new gate dielectric material HfTiON film

A new gate dielectric material HfTiON is deposited by reactive co-sputtering of Hf and Ti targets in N2/O2 ambient, followed by annealing in N2 at 600 ℃ and 800 ℃ respectively for 2 min. Capacitance-voltage and gate-leakage properties are characterized and compared for different anneal conditions. The results indicate that the sample annealed at 800 ℃ exhibits lower interface-state and oxide-charge densities, and better device reliability. This is attributed to the fact that the rapid thermal annealing at the higher temperature of 800 ℃ can effectively remove the damage-induced precipitation, forming a hardened dielectric/Si interface with high reliability.

Annealing before gate metal deposition related noise performance in AlGaN/GaN HEMTs

For a further improvement of the noise performance in A1GaN/GaN HEMTs, reducing the relatively high gate leakage current is a key issue. In this paper, an experiment was carried out to demonstrate that one method during the device fabrication process can lower the noise. Two samples were treated differently after gate recess etching： one sample was annealed before metal deposition and the other sample was left as it is. From a comparison of their Ig-Vg characteristics, a conclusion could be drawn that the annealing can effectively reduce the gate leakage current. The etching plasma-induced damage removal or reduction after annealing is considered to be the main factor responsible for it. Evidence is given to prove that annealing can increase the Schottky barrier height. A noise model was used to verify that the annealing of the gate recess before the metal deposition is really effective to improve the noise performance of AIGaN/GaN HEMTs.

Study and modeling of the transport mechanism in a Schottky diode on the basis of a GaAs semiinsulator

The current through a metal-semiconductor junction is mainly due to the majority carriers. Three distinctly different mechanisms exist in a Schottky diode： diffusion of the semiconductor carriers in metal, thermionic emission-diffusion （TED） of carriers through a Schottky gate, and a mechanical quantum that pierces a tunnel through the gate. The system was solved by using a coupled Poisson-Boltzmann algorithm. Schottky BH is defined as the difference in energy between the Fermi level and the metal band carrier majority of the metal--semiconductor junction to the semiconductor contacts. The insulating layer converts the MS device in an MIS device and has a strong influence on its current-voltage （I-V） and the parameters ofa Schottky barrier from 3.7 to 15 eV. There are several possible reasons for the error that causes a deviation of the ideal behaviour of Schottky diodes with and without an interracial insulator layer. These include the particular distribution of interface states, the series resis- tance, bias voltage and temperature. The GaAs and its large concentration values of trap centers will participate in an increase in the process ofthermionic electrons and holes, which will in turn act on the I-V characteristic of the diode, and an overflow maximum value [NT = 3 × 10^20] is obtained. The I-V characteristics of Schottky diodes are in the hypothesis of a parabolic summit.