Combined Novel Gate Level Model and Critical Primary Input Sharing for Genetic Algorithm Based Maximum Power Supply Noise Estimation

A gate level maximum power supply noise （PSN） model is defined that captures both IR drop and di/dt noise effects. Experimental results show that this model improves PSN estimation by 5.3% on average and reduces computation time by 10.7% compared with previous methods. Furthermore,a primary input critical factor model that captures the extent of primary inputs＇ PSN contribution is formulated. Based on these models,a novel niche genetic algorithm is proposed to estimate PSN more effectively. Compared with general genetic algorithms, this novel method can achieve up to 19.0% improvement on PSN estimation with a much higher convergence speed.

ARCHITECTURE MODEL AND RESOURCE GRAPH BUILDING ALGORITHM FOR DETAILED FPGA ARCHITECTURE DESIGN

This paper addresses the issue of designing the detailed architectures of Field-Programmable Gate Arrays(FPGAs), which has a great impact on the overall performances of an FPGA in practice. Firstly, a novel FPGA architecture description model is proposed based on an easy-to-use file format known as YAML. This format permits the description of any detailed architecture of hard blocks and channels. Then a general algorithm of building FPGA resource graph is presented. The proposed model is scalable and capable of dealing with detailed architecture design and can be used in FPGA architecture evaluation system which is developed to enable detailed architecture design. Experimental results show that a maximum of 16.36% reduction in total wirelength and a maximum of 9.34% reduction in router effort can be obtained by making very little changes to detailed architectures, which verifies the necessity and effectiveness of the proposed model.

Statistical Modeling of Gate Capacitance Variations Induced by Random Dopants in Nanometer MOSFETs Reserving Correlations

We consider intrinsic gate capacitance variations due to random dopants in the nanometer metal oxide semi- conductor field effect transistor （MOSFET） channel. The variations of total gate capacitance and gate transcapacitances are investigated and the strong correlations between the trans-capacitance variations are discovered. A simple statistical model is proposed for accurately capturing total gate capacitance variability based on the correlations. The model fits very well with the Monte Carlo simulations and the average errors are -0.033% for n-type metal-oxide semiconductor and -0.012% for p-type metal-oxide semiconductor, respectively. Our simulation studies also indicate that, owing to these correlations, the total gate capacitance variability will not dominate in gate capacitance variations.

Neonatal ventral hippocampal lesion as a valid model of schizophrenia： evidence from sensory gating study

Background The neonatal ventral hippocampal lesion （NVHL） rat model has been proposed as an experimental model for schizophrenia. NVHL rats display impaired central nervous system （CNS） inhibition, which may lead to a phenomenon similar to P50 sensory gating deficits observed in schizophrenic patients. In this study, we investigated whether sensory gating deficits occurred in the NVHL rat as a model for schizophrenia. Methods We created the NVHL rat model using ibotenate. The P20 and N40 were measured to assess sensory response and gating in NVHL and sham rats. Epidural electrodes recorded evoked potentials （EPs）, from which latencies, amplitudes, difference scores （$1-$2）, and gating ratios （$2/$1） were assessed. Results Compared with sham controls, prolonged S1 N40 latency and decreased S2 N40 amplitude were detected in the NVHL group. In neither difference scores nor gating ratios, a significant difference was found between NVHL group and sham controls. Conclusions NVHL rats may be a valid animal model for schizophrenia. This strategy will be useful in future neurobiological studies investigating the etiology of schizophrenia.

On modeling the digital gate delay under process variation

To achieve a characterization method for the gate delay library used in block based statistical static timing analysis with neither unacceptably poor accuracy nor forbiddingly high cost,we found that general-purpose gate delay models are useful as intermediaries between the circuit simulation data and the gate delay models in required forms.In this work,two gate delay models for process variation considering different driving and loading conditions are proposed.From the testing results,these two models,especially the one that combines effective dimension reduction（EDR） from statistics society with comprehensive gate delay models,offer good accuracy with low characterization cost,and they are thus competent for use in statistical timing analysis（SSTA）.In addition, these two models have their own value in other SSTA techniques.

Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO_2/high-k gate stacked dielectric

A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of great importance. In this paper we have explored the gate tunneling current of a double gate junctionless transistor（DGJLT） for the first time through an analytical model, to meet the future requirement of expected high-k gate dielectric material that could replace SiO2. We therefore present the high-k gate stacked architecture of the DGJLT to minimize the gate tunneling current. This paper also demonstrates the impact of conduction band offset,workfunction difference and k-values on the tunneling current of the DGJLT.

On essential topics of BYY harmony learning： Current status, challenging issues, and gene analysis applications

As a supplementary of [Xu L. Front. Electr. Electron. Eng. China, 2010, 5（3）： 281-328], this paper outlines current status of efforts made on Bayesian Ying- Yang （BYY） harmony learning, plus gene analysis appli- cations. At the beginning, a bird＇s-eye view is provided via Gaussian mixture in comparison with typical learn- ing algorithms and model selection criteria. Particularly, semi-supervised learning is covered simply via choosing a scalar parameter. Then, essential topics and demand- ing issues about BYY system design and BYY harmony learning are systematically outlined, with a modern per- spective on Yin-Yang viewpoint discussed, another Yang factorization addressed, and coordinations across and within Ying-Yang summarized. The BYY system acts as a unified framework to accommodate unsupervised, su- pervised, and semi-supervised learning all in one formu- lation, while the best harmony learning provides novelty and strength to automatic model selection. Also, mathe- matical formulation of harmony functional has been ad- dressed as a unified scheme for measuring the proximity to be considered in a BYY system, and used as the best choice among others. Moreover, efforts are made on a number of learning tasks, including a mode-switching factor analysis proposed as a semi-blind learning frame- work for several types of independent factor analysis, a hidden Markov model （HMM） gated temporal fac- tor analysis suggested for modeling piecewise stationary temporal dependence, and a two-level hierarchical Gaus- sian mixture extended to cover semi-supervised learning, as well as a manifold learning modified to facilitate au- tomatic model selection. Finally, studies are applied to the problems of gene analysis, such as genome-wide asso- ciation, exome sequencing analysis, and gene transcrip- tional regulation.

Load-pull measurement analysis of AlGaN/GaN HEMT taking into account number of gate fingers

This paper investigates load-pull measurement of AlGaN/GaN high electron mobility transistors（HEMTs） at different numbers of gate fingers.Scalable small-signal models are extracted to analyze the relationship between each model＇s parameters and the number of device＇s gate fingers.The simulated S-parameters from the small-signal models are compared with the reflection coefficients measured from the load-pull measurement system at X-band frequencies of 8.8 and 10.4 GHz.The dependency between the number of device＇s gate fingers and load-pull characterization is presented.