A Novel CMOS Current Mode Bandgap Reference

A novel CMOS bandgap reference is presented. The output reference of this new current mode structure can be set to an arbitrary value above the bandgap voltage of silicon,avoiding offset in application. It also overcomes the systematic mismatch of conventional current mode bandgap references. The proposed bandgap reference has been implemented in UMC 0.18μm mixed mode technology. Under the supply voltage of 1.6V, the proposed bandgap reference provides an output reference of 1.45V and consumes 27μA of supply current. Using no curvature compensation,it can reach a temperature coefficient of 23ppm/℃ from 30 to 150℃ with a line regulation of 2. 1mV/V from 1.6 to 3V and a PSRR of 40dB at DC frequency. The chip area of the bandgap reference （without pad） is 0. 088mm^2.

COMPARISON AND EVALUATION OF CURRENT REFERENCE GENERATION STRATEGIES FOR ACTIVE POWER FILTERS IN THREE-PHASE FOUR-WIRE SYSTEMS

For three phase four-wire active power filters （APFs）, several typical power theories and corresponding current reference generation strategies are induced, p-q, d-q, unify power factor （UPF） and instantaneous active current （IAC） methods are analyzed and compared with each other. The interpretation of active and reactive currents in non-sinusoidal and unbalanced three-phase four-wire systems is given based on the generalized instantaneous reactive power theory. The performance and the characteristic are evaluated, and the application conditions of current reference generation strategies are concluded. Simulation results under different source voltages and loads verify the evaluation result.

Analysis and design of high linearity current reference for current mode circuits

A complementary metal-oxide-semiconductor transistor （CMOS） voltage-to-current（VTC）converter with high linearity for current-mode analog and digital integrated circuits is described. A high gain operational amplifier （OPA） is utilized to form negative feedback. A proportional to absolute temperature （PTAT） current reference with transistors operated in a weak inversion is used as the bias circuit. The resistor and the OPA nonlinearity behavior are analyzed in detail. By optimizing parameters in OPA and adopting a small voltage coefficient polysilicon resistor as a linear device, a high linearity is achieved. The circuit is implemented in a standard 0. 6 μm CMOS technology. The low frequency gain of the OPA exceeds 90 dB. The test results indicate that the total harmonic distortion （THD）is 0. 000 2%. The common-mode input linearity range is 0 to 2. 6 V. Correspondingly, the output current range is 50 to 426μA. The sensitivity of the PTAT current reference to Vdd is approximately 0. 021 7. The chip consumes a power of less than 1.3 mW for a 5 V supply, and occupies an area of 0. 112 mm^2.

A novel low-voltage high precision current reference based on subthreshold MOSFETs

A novel topology low-voltage high precision current reference based on subthreshold Metal-Oxide-Semiconductor Field Effect Transistors （MOSFETs） is presented. The circuit achieves a temperature-independent reference current by a proper combination current of two first-order temperature-compensation current references, which exploit the temperature characteristics of integrated poly2 resistors and the 1- V transconductance characteristics of MOSFET operating in the subthreshold region. The circuit, designed with the 1 st silicon 0.35 μm standard CMOS logic process technology, exhibits a stable current of about 2.25 μA with much low temperature coefficient of 3 × 10^-4μA/℃ in the temperature range of-40-150 ℃ at 1 V supply voltage, and also achieves a better power supply rejection ratio （PSRR） over a broad frequency. The PSRR is about -78 dB at DC and remains -42 dB at the frequency higher than 10 MHz. The maximal process error is about 6,7% based on the Monte Carlo simulation. So it has good process compatibility.

An Integrated Drive for Two PMSMs Involved Automotive Applications and Development of Current Reference Expanded Two Arm Modulation Technique

A five leg inverter (FLI) control is incorporated to drive two independent rated permanent magnet synchronous motors (PMSMs) for automotive applications. Literature evidences many attempts of employing the FLI for controlling two general purpose/special motors, where variety of modulation techniques has been practiced for performance enhancement. Also in these cases one leg of inverter is common to both the motors. The expanded two arm modulation (ETAM) has been generally engaged in FLI. In ETAM the percentage voltage utilization factor (VUF) is calculated based on “αmax”, where “αmax” is the maximum modulation index and equal to and hence it restricts the VUF to 50%. This makes the FLI drives to use the dc link in inefficient way, which is due to the fact that conventional ETAM works with voltage reference. This paper modifies the ETAM in an ingenious way to improve the VUF further through current reference. In addition, the developed current reference expanded two arm modulation (CRETAM) minimizes the current harmonics and torque ripple as well. A detailed comparison of the CRETAM with the conventional ETAM and the competent digital counterpart, space vector pulse width modulation (SVPWM), is also presented. The enhancement in VUF, torque ripple minimization and current total harmonic distortion (THD) reduction are found in the MATLAB based simulation results.

Novel High PSRR Current Reference Based on Subthreshold MOSFETs

This paper takes full advantages of the I-V transconductance characteristics of metal-oxide semiconductor field effect transistor （MOSFET） operating in the subthreshold region and the enhancement pre-regulator technique with the high gain negative feedback loop. The proposed reference circuit, designed with the SMIC 0.18 μm standard complementary metal-oxide semiconductor （CMOS） logic process technology, exhibits a stable current of about 1.701 μA with much low temperature coefficient （TC） of 2.5×10^-4μA/℃ in the temperature range of-40 to 150℃ at 1.5 V supply voltage, and also achieves a best PSRR over a broad frequency. The PSRR is about - 126 dB at DC frequency and remains -92 dB at the frequency higher 100 MHz. Moreover the proposed reference circuit operates stably at the supply voltage higher 1.2 V and has good process compatibility.

A New 1-V Second-Order Temperature-Compensated Current Reference

A new bipolar temperature-compensated current reference is proposed. The first-order temperature compensation is achieved by the idea of self temperature-compensation configuration exploiting the temperature coefficient of a combined resistor. The second-order compensation employs a VBE-tracking thermal-startup technique to obtain improved temperature performance. The proposed circuit can operate down to a 1-V supply. A temperature coefficient of 46.6×10?6/℃ [0, 100℃] at a 1-V supply and a supply regulation of 0.036%/V at 25℃ are achieved. Compared with present works, the proposed circuit shows better results of the temperature coefficient and supply regulation. The current matching issue frequently encountered in current references is also discussed in detail.

A New CMOS Current Reference with High Order Temperature Compensation

A new high order CMOS temperature compensated current reference is proposed in this paper, which is accomplished by two first order temperature compensation current references. The novel circuit exploits the temperature characteristics of integrated-circuit resistors and gate-source voltage of MOS transistors working in weak inversion. The proposed circuit, designed with a 0.6 Izm standard CMOS technology, gives a good temperature coefficient of 31ppm/℃ [-50-100℃] at a 1.8V supply, and also achieves line regulation of 0.01%/V and-120dB PSR at 1 MHz. Comparing with other presented work, the proposed circuit shows better temperature coefficient and Line regulation.

A CMOS Voltage Reference Based on V_(GS) and ΔV_(GS) in the Weak Inversion Region

A CMOS voltage reference, which is based on VGs and/x ΔGS in the weak inversion region, has been designed and implemented in standard 0.6μm CMOS technology. No diodes and parasitic bipolar junction transistors （BJTs） are used. The proposed voltage reference uses a current-mode topology by summing a PTAT current and a CTAT current into a re- sistor to generate the required reference voltage. It can also provide more than one reference voltage output, which is quite suitable for systems requiring many different reference voltages simultaneously. The occupied chip area is 0. 023mm^-2 . The operation supply voltage is from 2.5 to 6V, and the maximum supply current is 8.25μA. The designed three different out- puts are respectively about 203mV, 1.0V, and 2.05V at room temperature when the supply voltage is 4V. The circuit achieves a temperature coefficient of 31ppm/℃ in the temperature range of 0 to 100℃ and an average line regulation of ± 0. 203%/V. The voltage reference has been successfully applied in a white LED backlight driver chip.

IC Implementation of a Programmable CMOS Voltage Reference

A new approach for the design and implementation of a programmable voltage reference based on an improved current mode bandgap voltage reference is presented. The circuit is simulated and fabricated with Chartered 0. 35μm mixed-signal technology. Measurements demonstrate that the temperature coefficient is ± 36. 3ppm/℃ from 0 to 100℃ when the VID inputs are 11110.As the supply voltage is varied from 2.7 to 5V, the voltage reference varies by about 5mV. The maximum glitch of the transient response is about 20mV at 125kHz. Depending on the state of the five VID inputs,an output voltage between 1.1 and 1.85V is programmed in increments of 25mV.

New Curvature-Compensated CMOS Bandgap Voltage Reference

A novel curvature-compensated CMOS bandgap voltage reference is presented. The reference utilizes two first order temperature compensations generated from the nonlinearity of the finite current gain β of vertical pnp bipolar transistor. The proposed circuit, designed in a standard 0.18 μm CMOS process, achieves a good temperature coefficient of 2.44 ppm/℃ with temperature range from --40℃ to 85 ℃, and about 4 mV supply voltage variation in the range from 1.4 V to 2.4 V. With a 1.8 V supply voltage, the power supply rejection ratio is -56dB at 10MHz.

The improved PAC method for a three-phase PWM grid-connected inverter

In this paper, a vector regulating principle of the phase and amplitude control PAC method for three-phase grid-connected inverters is presented.To solve the problem of heavy inrush current and slow dynamic response when system starts up, the starting voltage prediction control and the current feed-forward control are proposed and used, which improve the dynamic performance of the system in the PAC.The experimental results carried out on a three-phase grid-connected inverter proved the validity of the proposed method.

Curvature Compensated CMOS Bandgap Reference with Novel Process Variation Calibration Technique

A lowtemperature coefficient（ TC） bandgap reference（ BGR） with novel process variation calibration technique is proposed in this paper. This proposed calibration technique compensating both TC and output value of BGR achieves fine adjustment step towards the reference voltage,while keeping optimal TC by utilizing large resistance to help layout match. The high-order curvature compensation realized by poly and p-diffusion resistors is introduced into the design to guarantee the temperature characteristic. Implemented in 180 nm technology,the proposed BGR has been simulated to have a power supply rejection ratio（ PSRR） of 91 dB@100 Hz. The calibration technique covers output voltage scope of 0. 49 V-0. 56 Vwith TC of 9. 45 × 10^（-6）/℃-9. 56 × 10^（-6）/℃ over the temperature range of-40 ℃-120 ℃. The designed BGR provides a reference voltage of 500 mV,with measured TC of 10. 1 × 10^（-6）/℃.

一种高PSRR低温漂无运放带隙基准

针对无运放带隙基准电压源温度特性及电源抑制比差的问题,设计一种高电源抑制比、低温漂的无运放带隙基准电路。该电路通过电流镜进行钳位,避免运算放大器失调电压对输出基准的影响,利用晶体管栅极与三极管基极生成稳定的补偿电流,以降低基准电压的高阶温度系数,输出端采用共源共栅结构提高电源抑制比。基于SMIC 0.18μm BCD工艺在Cadence环境下对电路进行仿真,仿真结果表明:在-40~125℃范围内,电路的温度系数为3.187×10^(-6)/℃,10 Hz时电源抑制比为-88.6 dB,1 MHz时电源抑制比为-50.2 dB。在考虑启动电路影响的情况下,电路在5 V电源下的静态电流为3.78μA,带隙基准的版图面积为160μm×183μm。可实现对基准电压高阶温度项的补偿,降低温度系数,并在没有滤波电容的条件下提高带隙基准的PSRR。

一种新型带曲率补偿的带隙基准

针对传统带隙基准存在温度漂移大以及电源抑制比低的问题,提出了一种新型的带曲率补偿的带隙基准电压源。采用基极电流补偿以及曲率补偿技术对传统带隙基准结构进行改进。设计了低失配改进电路、低温漂改进以及启动电路等。利用共源共栅电流镜技术和负反馈网络保证带隙基准输出电压,极大程度降低了运放失调电压对带隙基准电压的干扰,实现了低温漂特性。基于东部高科0.18μm BCD工艺,在Cadence Spectre下进行仿真。仿真结果表明:该带隙基准电路在-40~150℃温度范围内,输入电压为5 V,输出电压稳定在1.192 V;温度系数为4.84×10^(-6)/℃;在低频时电源抑制比为-78 dB。

基于参数辨识的永磁辅助同步磁阻电机电流无差拍控制

针对永磁辅助同步磁阻电机电感参数失配引起传统无差拍预测电流控制器受扰动的问题,该文提出一种电感参数自适应的无差拍预测电流控制方案。所提算法利用模型参考自适应系统对电感参数进行在线辨识,并将辨识结果代替控制器中的原始电感模型参数,以确保控制器的模型参数和电机实际参数相匹配,进而增强无差拍预测电流控制系统的鲁棒性。根据永磁辅助同步磁阻的数学模型,对电机本体进行了建模,以实现对所提算法的仿真验证。最后在以TMS320F28335控制器为核心的实验平台上进行了实验验证。仿真和实验结果均表明,当电机参数与模型参数不匹配时,所提算法相较于传统的无差拍预测电流控制算法在电流波动峰峰值、电流跟踪静差及系统鲁棒性方面都有明显的改善。

基于带隙基准的改进型像元共享CTIA红外读出电路设计

为了提高红外读出电路动态范围、增强红外成像质量,加入暗电流抑制模块电路,设计了一种四像元分时共享的电容反馈跨阻放大器(CTIA)和带隙基准源相互配合的高性能红外读出电路。通过带隙基准源产生两个基准电压586 mV和293 mV,其中293 mV基准电压值的温漂系数达到1.49×10-6/℃,可对分流管的栅极和源极提供稳定的电压偏置,实现对暗电流的精准撇除。结果表明,该电路可实现电流信号从10 pA~10 nA宽动态范围的积分电压读出,读出数据通过线性拟合,拟合优度R 2达到0.9992,说明电路性能良好。此研究未来可应用到线列和面阵的红外探测器中。

基于光伏动态电流参考值的两级式光伏并网系统低电压穿越控制策略

随着光伏接入容量的不断提升,电网电压跌落时光伏脱网会影响系统稳定运行,因此光伏系统应具备低电压穿越(LVRT)能力。然而,目前常用的两级式光伏并网系统LVRT控制策略存在光伏动态响应慢及控制效果受限于光伏P–U特性曲线的数学模型精度等问题,且未考虑局部阴影条件下的适用性。基于此,提出一种基于光伏动态电流参考值的LVRT控制策略。首先,在建立两级式光伏并网系统及光伏电池P–U特性数学模型的基础上,分别对目前常用的基于定直流母线电压和基于光伏P–U特性曲线的LVRT控制的原理及不足进行了分析。其次,针对前级boost电路的控制构造了具有自适应收敛特性的光伏输出电流动态参考值以对光伏工作点进行直接调整。该策略无需对光伏P–U特性曲线数学模型进行求解,避免求解误差的同时加快了光伏动态响应速度。此外,在最大功率跟踪(MPPT)算法中引入故障解耦模块,在电网低电压故障期间对MPPT输出电压参考值进行锁定,避免MPPT无效运算带来的电压参考值偏移,使系统在故障结束时能以最快速度恢复至最大功率点。最后,通过仿真将所提策略与目前常用的基于定直流母线电压和基于光伏P–U特性曲线的LVRT控制策略在多种环境条件下进行对比。仿真结果表明:与定直流母线电压控制策略相比,所提策略下光伏动态响应快;与现有基于光伏P–U特性曲线的控制策略相比,所提策略不受P–U特性误差的影响,在辐照度变化尤其局部阴影条件下均能很好地实现低电压穿越。

基于参考电流增量法的感应分流器校验方法

感应分流器具有高准确度和高稳定性的电流比例,在电流互感器检定领域有着广泛的应用。文中提出了一种基于参考电流增量法原理的感应式分流器校验方法,文中介绍了参考电流增量法的基本原理;分析了参考电流互感器和差值电流测量线路的设计原理;搭建了感应分流器自校验的实验线路;对研制的双级感应分流器在50 Hz~1 kHz频率范围进行了校验,并对校验结果进行了不确定度分析。实验结果表明,在50 Hz~1 kHz频率范围内,双级感应分流器比值差测量合成标准不确定度优于5×10^(-8) A/A,相位差测量合成标准不确定度优于1×10^(-7) rad。

附带STATCOM的HVDC系统改进参考电压控制法

在弱交流系统下对于附带有STATCOM的电网换相换流器高压直流输电(Line Commutated Converter based High Voltage Direct Current, LCC-HVDC)系统,存在着LCC逆变站与STATCOM之间耦合导致LCC-HVDC系统的稳定裕度下降问题,这会减弱LCC-HVDC抑制换相失败的能力。此外,HVDC控制环节之中的电压指令电流控制(voltage dependent current order limiter, VDCOL)环节的输出电流指令大幅剧烈波动还有几率会导致HVDC系统在首次换相失败之后发生后续换相失败。针对上述问题提出了一种“改进参考电压”的思想,对STATCOM和VDCOL的参考电压与输入电压分别进行修正。首先在STATCOM原本的参考电压经过一个“虚拟电抗”之后得到一个新的参考电压,通过这个改进参考电压弱化了STATCOM电压外环控制模块与LCC逆变站的耦合,减小了交流系统等效阻抗的大小,提升了系统对干扰的抵抗能力。然后对VDCOL的输入电压进行改进,新的改进输入电压改善了故障后VDCOL输出电流指令的大幅剧烈波动情况。最后通过三个层次的对照试验,验证了所提方法的有效性。