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Fabrication and characterization of groove-gate MOSFETs based on a self-aligned CMOS process 被引量:1
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作者 马晓华 郝跃 +6 位作者 孙宝刚 高海霞 任红霞 张进城 张金凤 张晓菊 张卫东 《Chinese Physics B》 SCIE EI CAS CSCD 2006年第1期195-198,共4页
N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process have been fabricated and characterized. For the devices with channel length of 140nm, the measured drain induced barrier lowering (DIBL) was 6... N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process have been fabricated and characterized. For the devices with channel length of 140nm, the measured drain induced barrier lowering (DIBL) was 66mV/V for n-MOSFETs and 82mV/V for p-MOSFETs. The substrate current of a groove-gate n-MOSFET was 150 times less than that of a conventional planar n-MOSFET, These results demonstrate that groove-gate MOSFETs have excellent capabilities in suppressing short-channel effects. It is worth emphasizing that our groove-gate MOSFET devices are fabricated by using a simple process flow, with the potential of fabricating devices in the sub-100nm range. 展开更多
关键词 SELF-ALIGNED groove-gate MOSFETs DIBL short-channel effects
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