This paper deals with the technology of using comb filters for FIR Decimation in Digital Signal Processing. The process of decreasing the sampling frequency of a sampled signal is called decimation. In the usage of de...This paper deals with the technology of using comb filters for FIR Decimation in Digital Signal Processing. The process of decreasing the sampling frequency of a sampled signal is called decimation. In the usage of decimating filters, only a portion of the out-of-pass band frequencies turns into the pass band, in systems wherein different parts operate at different sample rates. A filter design, tuned to the aliasing frequencies all of which can otherwise steal into the pass band, not only provides multiple stop bands but also exhibits computational efficiency and performance superiority over the single stop band design. These filters are referred to as multiband designs in the family of FIR filters. The other two special versions of FIR filter designs are Halfband and Comb filter designs, both of which are particularly useful for reducing the computational requirements in multirate designs. The proposed method of using Comb FIR decimation procedure is not only efficient but also opens up a new vista of simplicity and elegancy to compute Multiplications per Second (MPS) and Additions per Second (APS) for the desired filter over and above the half band designs.展开更多
This paper presents the design considerations and implementation of an area-efficient interpolator suitable for a delta-sigma D/A converter. In an effort to reduce the area and design complexity, a method for designin...This paper presents the design considerations and implementation of an area-efficient interpolator suitable for a delta-sigma D/A converter. In an effort to reduce the area and design complexity, a method for designing an FIR filter as a tapped cascaded interconnection of identical subfilters is modified. The proposed subfilter structure further minimizes the arithmetic number. Experimental results show that the proposed interpolator achieves the design specification,exhibiting high performance and hardware efficiency,and also has good noise rejection capability. The interpolation filter can be applied to a delta-sigma DAC and is fully functional.展开更多
This paper describes a low-power low-cost 24-bit ∑-△ digital-to-analog converter （DAC） for portable digital-audio applications. The interpolation filter uses a no-multiplier scheme to implement the arithmetic unit...This paper describes a low-power low-cost 24-bit ∑-△ digital-to-analog converter （DAC） for portable digital-audio applications. The interpolation filter uses a no-multiplier scheme to implement the arithmetic units and reading-writing common storage scheme for the delay-line to significantly reduce the die area. A 15-level quantizer, third-order, single-stage ∑-△ modulator is employed to reduce the passband quantization noise, relax the out-of-band filtering requirements, and enhance immunity to clock jitter. A data weighted averaging algorithm is used to mitigate the nonlinearity caused by capacitor mismatch. A direct charge transfer switched-capacitor low-pass filter （DCT-SC LPF） is used to reconstruct the analog signal to reduce the kTIC noise and capacitor mismatch effect with a small increase of the power dissipation. The chip was fabricated in the SMIC 0.13 μm 1P5M CMOS process. The cell area of the digital part is 0.056 mm^2 and the total area of the analog part is 0.34 mm^2. The supply voltage is 1.2 V for the digital circuit and 3.3 V for the analog circuit. The power consumption of the analog part is 3.5 mW. The audio DAC achieves a 100 dB dynamic range and an 84 dB peak signal-to-noise-plus-distortion ratio over a 20 kHz passband. The results show that these performances are good enough for high quality portable audio applications.展开更多
文摘This paper deals with the technology of using comb filters for FIR Decimation in Digital Signal Processing. The process of decreasing the sampling frequency of a sampled signal is called decimation. In the usage of decimating filters, only a portion of the out-of-pass band frequencies turns into the pass band, in systems wherein different parts operate at different sample rates. A filter design, tuned to the aliasing frequencies all of which can otherwise steal into the pass band, not only provides multiple stop bands but also exhibits computational efficiency and performance superiority over the single stop band design. These filters are referred to as multiband designs in the family of FIR filters. The other two special versions of FIR filter designs are Halfband and Comb filter designs, both of which are particularly useful for reducing the computational requirements in multirate designs. The proposed method of using Comb FIR decimation procedure is not only efficient but also opens up a new vista of simplicity and elegancy to compute Multiplications per Second (MPS) and Additions per Second (APS) for the desired filter over and above the half band designs.
文摘This paper presents the design considerations and implementation of an area-efficient interpolator suitable for a delta-sigma D/A converter. In an effort to reduce the area and design complexity, a method for designing an FIR filter as a tapped cascaded interconnection of identical subfilters is modified. The proposed subfilter structure further minimizes the arithmetic number. Experimental results show that the proposed interpolator achieves the design specification,exhibiting high performance and hardware efficiency,and also has good noise rejection capability. The interpolation filter can be applied to a delta-sigma DAC and is fully functional.
文摘This paper describes a low-power low-cost 24-bit ∑-△ digital-to-analog converter （DAC） for portable digital-audio applications. The interpolation filter uses a no-multiplier scheme to implement the arithmetic units and reading-writing common storage scheme for the delay-line to significantly reduce the die area. A 15-level quantizer, third-order, single-stage ∑-△ modulator is employed to reduce the passband quantization noise, relax the out-of-band filtering requirements, and enhance immunity to clock jitter. A data weighted averaging algorithm is used to mitigate the nonlinearity caused by capacitor mismatch. A direct charge transfer switched-capacitor low-pass filter （DCT-SC LPF） is used to reconstruct the analog signal to reduce the kTIC noise and capacitor mismatch effect with a small increase of the power dissipation. The chip was fabricated in the SMIC 0.13 μm 1P5M CMOS process. The cell area of the digital part is 0.056 mm^2 and the total area of the analog part is 0.34 mm^2. The supply voltage is 1.2 V for the digital circuit and 3.3 V for the analog circuit. The power consumption of the analog part is 3.5 mW. The audio DAC achieves a 100 dB dynamic range and an 84 dB peak signal-to-noise-plus-distortion ratio over a 20 kHz passband. The results show that these performances are good enough for high quality portable audio applications.
