A design of super-orthogonal space-time trellis codes （SOSTTCs） based on the trace criterion （TC） is proposed for improving the design of SOSTTCs. The shortcomings of the rank and determinant criteria based design...A design of super-orthogonal space-time trellis codes （SOSTTCs） based on the trace criterion （TC） is proposed for improving the design of SOSTTCs. The shortcomings of the rank and determinant criteria based design and the advantages of the TC-based design are analyzed. The optimization principle of four factors is presented, which includes the space-time block coding （STBC） scheme, set partitioning, trellis structure, and the assignment of signal subsets and STBC schemes in the trellis. According to this principle, systematical and handcrafted design steps are given in detail. By constellation expansion, the code performance can be further improved. The code design results are given, and the new codes outperform others in the simulation.展开更多
Digital low-density parity-check(LDPC) decoders can hardly meet the power-limits brought by the new application scenarios. The analog LDPC decoder, which is an application of the analog computation technology, is cons...Digital low-density parity-check(LDPC) decoders can hardly meet the power-limits brought by the new application scenarios. The analog LDPC decoder, which is an application of the analog computation technology, is considered to have the potential to address this issue to some extent. However, due to the lack of automation tools and analog stopping criteria, the analog LDPC decoders suffer from costly handcraft design and additional decoding delay, and are not feasible to practical applications. To address these issues, a decoder architecture using reusable building blocks is designed to lower the handcraft design, and a probability stopping criterion that is specially designed for analog decoder is further planned and implemented to reduce the decoding delay. Then, a(480,240) CMOS analog LDPC decoder is designed and fabricated in a 0.35-μm CMOS technology. Experimental results show that the decoder prototype can achieve 50 Mbps throughput when the power consumption is about 86.3m W, and the decoding delay can be reduced by at most 93% compared with using the preset maximum decoding delay in existing works.展开更多
文摘A design of super-orthogonal space-time trellis codes （SOSTTCs） based on the trace criterion （TC） is proposed for improving the design of SOSTTCs. The shortcomings of the rank and determinant criteria based design and the advantages of the TC-based design are analyzed. The optimization principle of four factors is presented, which includes the space-time block coding （STBC） scheme, set partitioning, trellis structure, and the assignment of signal subsets and STBC schemes in the trellis. According to this principle, systematical and handcrafted design steps are given in detail. By constellation expansion, the code performance can be further improved. The code design results are given, and the new codes outperform others in the simulation.
基金supported in part by the National Natural Science Foundation of China(No.61601027)the Opening Fund of the Space Objective Measure Key Laboratory(No.2016011)
文摘Digital low-density parity-check(LDPC) decoders can hardly meet the power-limits brought by the new application scenarios. The analog LDPC decoder, which is an application of the analog computation technology, is considered to have the potential to address this issue to some extent. However, due to the lack of automation tools and analog stopping criteria, the analog LDPC decoders suffer from costly handcraft design and additional decoding delay, and are not feasible to practical applications. To address these issues, a decoder architecture using reusable building blocks is designed to lower the handcraft design, and a probability stopping criterion that is specially designed for analog decoder is further planned and implemented to reduce the decoding delay. Then, a(480,240) CMOS analog LDPC decoder is designed and fabricated in a 0.35-μm CMOS technology. Experimental results show that the decoder prototype can achieve 50 Mbps throughput when the power consumption is about 86.3m W, and the decoding delay can be reduced by at most 93% compared with using the preset maximum decoding delay in existing works.
