Research on Multi-Core Processor Analysis for WCET Estimation

Real-time system timing analysis is crucial for estimating the worst-case execution time(WCET)of a program.To achieve this,static or dynamic analysis methods are used,along with targeted modeling of the actual hardware system.This literature review focuses on calculating WCET for multi-core processors,providing a survey of traditional methods used for static and dynamic analysis and highlighting the major challenges that arise from different program execution scenarios on multi-core platforms.This paper outlines the strengths and weaknesses of current methodologies and offers insights into prospective areas of research on multi-core analysis.By presenting a comprehensive analysis of the current state of research on multi-core processor analysis for WCET estimation,this review aims to serve as a valuable resource for researchers and practitioners in the field.

An On-Line Scheduler over Hard Real-Time Communication System

By thorough research on the prominent periodic and aperiodic scheduling algorithms,anon-line hard real-time scheduler is presented,which is applicable to the scheduling of packets over a link.This scheduler,based on both Rate Monotonic,pinwheel scheduling algorithm Sr and Polling Serverscheduling algorithms,can rapidly judge the schedulability and then automatically generate a bus tablefor the scheduling algorithm to schedule the packets as the periodic packets.The implementation of thescheduler is simple and easy to use,and it is effective for the utilization of bus link.The orderly executionof the bus table can not only guarantee the performance of the hard real time but also avoid the blockageand interruption of the message transmission.So the scheduler perfectly meets the demand of hard real-time communication system on the field bus domain.

An integrated DBP for streams with （m, k）-firm real-time guarantee

(m, k)-firm real-time or weakly hard real-time (WHRT) guarantee is becoming attractive as it closes the gap between hard and soft (or probabilistic) real-time guarantee, and enables finer granularity of real-time QoS through adjusting m and k. For multiple streams with (m, k)-firm constraint sharing a single server, an on-line priority assignment policy based on the most recent k-length history of each stream called distance based priority (DBP) has been proposed to assign priority.In case of priority equality among these head-of-queue instances, Earliest Deadline First (EDF) is used. Under the context of WHRT schedule theory, DBP is the most popular, gets much attention and has many applications due to its straightforward priority assignment policy and easy implementation. However, DBP combined with EDF cannot always provide good performance, mainly because the initial DBP does not underline the rich information on deadline met/missed distribution,specially streams in various failure states which will travel different distances to restore success states. Considering how to effectively restore the success state of each individual stream from a failure state, an integrated DBP utilizing deadline met/missed distribution is proposed in this paper. Simulation results validated the performance improvement of this pro-posal.

A heuristic mixed real-time task allocation of virtual utilization in multi-core processor

Multi-core processor is widely used as the running platform for safety-critical real-time systems such as spacecraft,and various types of real-time tasks are dynamically added at runtime.In order to improve the utilization of multi-core processors and ensure the real-time performance of the system,it is necessary to adopt a reasonable real-time task allocation method,but the existing methods are only for single-core processors or the performance is too low to be applicable.Aiming at the task allocation problem when mixed real-time tasks are dynamically added,we propose a heuristic mixed real-time task allocation algorithm of virtual utilization VU-WF(Virtual Utilization Worst Fit)in multi-core processor.First,a 4-tuple task model is established to describe the fixedpoint task and the sporadic task in a unified manner.Then,a VDS(Virtual Deferral Server)for serving execution requests of fixed-point task is constructed and a schedulability test of the mixed task set is derived.Finally,combined with the analysis of VDS's capacity,VU-WF is proposed,which selects cores in ascending order of virtual utilization for the schedulability test.Experiments show that the overall performance of VU-WF is better than available algorithms,not only has a good schedulable ratio and load balancing but also has the lowest runtime overhead.In a 4-core processor,compared with available algorithms of the same schedulability ratio,the load balancing is improved by 73.9%,and the runtime overhead is reduced by 38.3%.In addition,we also develop a visual multi-core mixed task scheduling simulator RT-MCSS(open source)to facilitate the design and verification of multi-core scheduling for users.As the high performance,VU-WF can be widely used in resource-constrained and safety-critical real-time systems,such as spacecraft,self-driving cars,industrial robots,etc.

Credit Determination of Fibre Channel in Avionics Environment

Fibre channel （FC） is the main candidate architecture for ＂unified network＂. Flow control deals with the problem in which a device receives frames faster than it can process them. Credit is an important service parameter for fibre channel flow control. Configuring the credit reasonably can avoid buffer overflow in nodes. This paper derives the mathematic relationships among credit, bandwidth and message sets under real-time condition according as three main topologies of fibre channel, and proposes the credit determination and the optimal credit for typical message sets. This study is based on the features of hard real-time communications in avionics environment.

基于Bank地址的IABA冲突分析及优化

为了降低物联网应用中用于关键事务控制的硬实时任务的最坏情况响应时间(WCRT),提出了一个基于任务地址分布的bank冲突优化框架.该框架从以下两个方面改善硬实时任务的WCRT:借助任务访问缓存地址因素约束bank冲突条件,并借此收敛任务的最差情况执行时间(WCET);基于任务访问缓存的地址分布特征优化地址映射降低冲突延迟时间.实验结果表明,所提方法分别可提升平均18.15%的冲突延迟估值以及减少大约20%的冲突延迟时间.

Conceptual model of real-time IoT systems

We address a special kind of Internet of Things (IoT) systems that are also real-time. We call them real-time IoT (RT-IoT) systems. An RT-IoT system needs to meet timing constraints of system delay, clock synchronization, deadline, and so on. The timing constraints turn to be more stringent as we get closer to the physical things. Based on the reference architecture of IoT (ISO/IEC 30141), the RT-IoT conceptual model is established. The idea of edge subsystem is introduced. The sensing & con-trolling domain is the basis of the edge subsystem, and the edge subsystem usually must meet the hard real-time constraints. The model includes four perspectives, the time view, computation view, communication view, and control view. Each view looks, from a different angle, at how the time parameters impact an RT-IoT system.

Admission Control of VL in AFDX Under HRT Constraints

Avionics full duplex switched ethernet（AFDX） is a switched interconnection technology developed to provide reliable data exchange with strong data transmission time guarantees in internal communication of the spacecraft or aircraft.Virtual link（VL） is an important concept of AFDX to meet quality of service（QoS） requirements in terms of end-to-end message deadlines.A VL admission control algorithm in AFDX network under hard real-time（HRT） constraints is studied.Based on the scheduling prin-ciple of AFDX protocol,a packet scheduling scheme under HRT constraints is proposed,and after that an efficient VL admission control algorithm is presented.Analytical proof that the algorithm can effectively determine whether VL should be admitted is given.Finally simulative examples are presented to promote the conclusion.

Reducing the Upper Bound Delay by Optimizing Bank-to-Core Mapping

Nowadays, inter-task interferences are the main difficulty in analyzing the timing behavior of multicores. The timing predictable embedded multicore architecture MERASA, which allows safe worst-case execution time （WCET） estimations, has emerged as an attractive solution. In the architecture, WCET can be estimated by the upper bound delay （UBD） which can be bounded by the interference-aware bus arbiter （IABA） and the dynamic cache partitioning such as columnization or bankization. However, this architecture faces a dilemma between decreasing UBD and efficient shared cache utilization. To obtain tighter WCET estimation, we propose a novel approach that reduces UBD by optimizing bank-to-core mapping on the multicore system with IABA and the two-level partitioned cache. For this, we first present a new UBD computation model based on the analysis of inter-task interference delay, and then put forward the core-sequence optimization method of bank-to-core mapping and the optimizing algorithms with the minimum UBD. Experimental results demonstrate that our approach can reduce WCET from 4% to 37%.