Depth estimation system suitable for hardware design

Depth estimation is an active research area with the developing of stereo vision in recent years. It is one of the key technologies to resolve the large data of stereo vision communication. Now depth estimation still has some problems, such as occlusion, fuzzy edge, real-time processing, etc. Many algorithms have been proposed base on software, however the performance of the computer configurations limits the software processing speed. The other resolution is hardware design and the great developments of the digital signal processor （DSP）, and application specific integrated circuit （ASIC） and field programmable gate array （FPGA） provide the opportunity of flexible applications. In this work, by analyzing the procedures of depth estimation, the proper algorithms which can be used in hardware design to execute real-time depth estimation are proposed. The different methods of calibration, matching and post-processing are analyzed based on the hardware design requirements. At last some tests for the algorithm have been analyzed. The results show that the algorithms proposed for hardware design can provide credited depth map for further view synthesis and are suitable for hardware design.

Dynamic Power Dissipation Control Method for Real-Time Processors Based on Hardware Multithreading

In order to eliminate the energy waste caused by the traditional static hardware multithreaded processor used in real-time embedded system working in the low workload situation, the energy efficiency of the hardware multithread is discussed and a novel dynamic multithreaded architecture is proposed. The proposed architecture saves the energy wasted by removing idle threads without manipulation on the original architecture, fulfills a seamless switching mechanism which protects active threads and avoids pipeline stall during power mode switching. The report of an implemented dynamic multithreaded processor with 45 nm process from synthesis tool indicates that the area of dynamic multithreaded architecture is only 2.27% higher than the static one in achieving dynamic power dissipation, and consumes 1.3% more power in the same peak performance.

Study on the Gas Detonation Experimental System of Human Body Electrostatic Discharge

The modeling system of the gas detonation by the human body electrostatic discharge(ESD)in coal mine is developed successfully,and the body’s dynamic ESD model is established.To obtain a gas concentration causes by the explosions most easily in coal mine environment.The results provide an academic and experimental evidence for the safe electrostatic production and management in coal mine.The system adopts 77E58 as control core and the circuit optimized design,to take dual protection to the gas path and circuit of the system,systematic operation is safe and reliable.The experimental results show that the system can be carried out series of experiments of the human body ESD model detonating mixed gas,the measuring accuracy of gas concentration is 0.1%.And draws a conclusion that the gas concentration which causes the explosions most easily is 8.7%,but not the higher gas concentration is,the more explosive is.

Mitigating adjacent channel interference in vehicular communication systems

In the last few decades, dedicated wireless channels were specifically allocated to enable the development and implementation of vehicular communication systems. The two main protocol stacks, the WAVE stan- dards proposed by the IEEE in the United States and the ETSI ITS-G5 in Europe, reserved 10 MHz wide channels in the 5.9 GHz spectrum band. Despite the exclusive use of these frequencies for vehicular com- munication purposes, there are still cross channel interference problems that have been widely reported in the literature. In order to mitigate these issues, this paper presents the design of a two-stage FIR low-pass filter, targeting the integration with a digital baseband receiver chain of a custom vehicular communications platform. The filter was tested, evaluated and optimized, with the simulation results proving the effectiveness of the proposed method and the low delay introduced in the overall operation of the receiver chain. 2016 Chongqing University of Posts and Telecommunications. Production and Hosting by Elsevier B.V. This is an open access article under the CC BY-NC-ND license

Hardware Design and Test of a Gear-Shifting Control System of a Multi-gear Transmission for Electric Vehicles

The performance of electric vehicles is affected by the shift quality of multi-gear transmission.The realization of dual-target tracking control requires the transmission control unit(TCU)to accurately measure and process the input signals of the gear-shifting control system and precisely control the drive motor torque and the position of shift motors.An electric-vehicle-dedicated TCU was designed to meet the above design requirements.Its function modules included a single-chip control circuit,shift position signal sampling circuit,signal conditioning circuit of the rotational speed and angle,controller area network communication circuit,and shift motor drive circuit.A hardware-in-the-loop simulation test system showed that the TCU design scheme met measurement accuracy requirements and coordinated the actions of the shift actuator and motor control unit to achieve fast and smooth shifting before the road test.The power interruption time of the shifting process was within 350 ms.The reliability of the TCU design was further verified in a 150,000-km vehicle road test.

Compact Real-time Simulator with Spatial-temporal Parallel Design for Large-scale Wind Farms

Real-time simulation of large-scale wind farms with detailed modeling can provide accurate insights into system transient behaviors,but entails challenges in computing resources.This paper develops a compact real-time simulator based on the field programmable gate array(FPGA)for large-scale wind farms,in which the spatial-temporal parallel design method is proposed to address the huge computation resource demand associated with detailed modeling.The wind farm is decoupled into several subsystems based on model consistency,and the electrical system and control system of each subsystem are solved in parallel.Both the module-level pipeline technique and superscalar pipeline technique are introduced to the wind farms’simulation to effectively improve the utilization of hardware resources.In case studies,real-time simulations of two modified wind farms are separately carried out on a single FPGA,including one with 13 permanent magnet synchronous generators under a time-step of 11µs,and the other with 30 squirrel-cage induction generators under a time-step of 8µs.Simulation tests,under different scenarios,are implemented to validate the numerical performance of the real-time simulator,and a comparison with the commercial tool PSCAD/EMTDC demonstrates the accuracy and effectiveness of the proposed design.

An Analysis and Validation Toolkit to Support the Undergraduate Course of Computer Organization and Architecture

As an important part of the computer organization and architecture(COA)course,the experiment teaching is generally about the computer system design.Students use the hardware description languages(HDLs)tools to implement the computer system on the Field Programmable Gate Array(FPGA)based platform.However,the HDLs tools are made for expert hardware engineers and the computer system is a very complex hardware project.It is hard for students to implement their computer system design in the limited lab hours.How to help students get the design validation and find the failure root is important in COA experiment teaching.To this end,an analysis and validation toolkit which is special for COA experiment teaching is designed.For two main steps of FPGA-based hardware design,waveform simulation and on-board testing,two packages were implemented for them respectively.The comparison results of using and not using our toolkit show it improves the effectiveness of experiment teaching greatly.