Scheduling Algorithm Based on Storage Capacity of Communication in Hardware/Software Integrated System

In this paper, the storage capacity of communication among cores and processors is taken into account and a maximum D-value-first algorithm is proposed. By improving the hardware parallelism in the task execution process, the maximum storage requirements for communication are minimized. Experimental results with various directed acyclic graph models showed that compared with the earliest-task-first algorithm, the storage requirements for communication were reduced by 22.46%, on average, while the average of makespan only increased by 0.82%,.

Hardware/software partitioning based on dynamic combination of maximum entropy and chaos optimization algorithm

This paper presents an algorithm that combines the chaos optimization algorithm with the maximum entropy ( COA-ME) by using entropy model based on chaos algorithm,in which the maximum entropy is used as the second method of searching the excellent solution. The search direction is improved by chaos optimization algorithm and realizes the selective acceptance of wrong solution. The experimental result shows that the presented algorithm can be used in the partitioning of hardware/software of reconfigurable system. It effectively reduces the local extremum problem,and search speed as well as performance of partitioning is improved.

New Approach for Hardware/Software Embedded System Conception Based on the Use of Design Patterns

This paper deals with a new hardware/software embedded system design methodology based on design pattern approach by development of a new design tool called smartcell. Three main constraints of embedded systems design process are investigated: the complexity, the partitioning between hardware and software aspects and the reusability. Two intermediate models are carried out in order to solve the complexity problem. The partitioning problem deals with the proposed hardware/software partitioning algorithm based on Ant Colony Optimisation. The reusability problem is resolved by synthesis of intellectual property blocks. Specification and integration of an intelligent controller on heterogeneous platform are considered to illustrate the proposed approach.

An Optimized Implementation of a Novel Nonlinear Filter for Color Image Restoration

Image processing is becoming more popular because images are being used increasingly in medical diagnosis,biometric monitoring,and character recognition.But these images are frequently contaminated with noise,which can corrupt subsequent image processing stages.Therefore,in this paper,we propose a novel nonlinear filter for removing“salt and pepper”impulsive noise from a complex color image.The new filter is called the Modified Vector Directional Filter(MVDF).The suggested method is based on the traditional Vector Directional Filter(VDF).However,before the candidate pixel is processed by the VDF,theMVDF employs a threshold and the neighboring pixels of the candidate pixel in a 3×3 filter window to determine whether it is noise-corrupted or noise-free.Several reference color images corrupted by impulsive noise with intensities ranging from 3%to 20%are used to assess theMVDF’s effectiveness.The results of the experiments show that theMVDF is better than the VDF and the Generalized VDF(GVDF)in terms of the PSNR(Peak Signal-to-Noise Ratio),NCD(Normalized Color Difference),and execution time for the denoised image.In fact,the PSNR is increased by 6.554%and 12.624%,the NCD is decreased by 20.273%and 44.147%,and the execution time is reduced by approximately a factor of 3 for the MVDF relative to the VDF and GVDF,respectively.These results prove the efficiency of the proposed filter.Furthermore,a hardware design is proposed for the MVDF using the High-Level Synthesis(HLS)flow in order to increase its performance.This design,which is implemented on the Xilinx ZynqXCZU9EG Field-ProgrammableGate Array(FPGA),allows the restoration of a 256×256-pixel image in 2 milliseconds(ms)only.

A Novel Hardware/Software Partitioning Method Based on Position Disturbed Particle Swarm Optimization with Invasive Weed Optimization

With the development of the design complexity in embedded systems, hardware/software （HW/SW） partitioning becomes a challenging optimization problem in HW/SW co-design. A novel HW/SW partitioning method based on position disturbed particle swarm optimization with invasive weed optimization （PDPSO-IWO） is presented in this paper. It is found by biologists that the ground squirrels produce alarm calls which warn their peers to move away when there is potential predatory threat. Here, we present PDPSO algorithm, in each iteration of which the squirrel behavior of escaping from the global worst particle can be simulated to increase population diversity and avoid local optimum. We also present new initialization and reproduction strategies to improve IWO algorithm for searching a better position, with which the global best position can be updated. Then the search accuracy and the solution quality can be enhanced. PDPSO and improved IWO are synthesized into one single PDPSO-IWO algorithm, which can keep both searching diversification and searching intensification. Furthermore, a hybrid NodeRank （HNodeRank） algorithm is proposed to initialize the population of PDPSO-IWO, and the solution quality can be enhanced further. Since the HW/SW communication cost computing is the most time-consuming process for HW/SW partitioning algorithm, we adopt the GPU parallel technique to accelerate the computing. In this way, the runtime of PDPSO-IWO for large-scale HW/SW partitioning problem can be reduced efficiently. Finally, multiple experiments on benchmarks from state-of-the-art publications and large-scale HW/SW partitioning demonstrate that the proposed algorithm can achieve higher performance than other algorithms.

An efficient GPU-based parallel tabu search algorithm for hardware/software co-design

Hardware/software partitioning is an essential step in hardware/software co-design.For large size problems,it is difficult to consider both solution quality and time.This paper presents an efficient GPU-based parallel tabu search algorithm(GPTS)for HW/SW partitioning.A single GPU kernel of compacting neighborhood is proposed to reduce the amount of GPU global memory accesses theoretically.A kernel fusion strategy is further proposed to reduce the amount of GPU global memory accesses of GPTS.To further minimize the transfer overhead of GPTS between CPU and GPU,an optimized transfer strategy for GPU-based tabu evaluation is proposed,which considers that all the candidates do not satisfy the given constraint.Experiments show that GPTS outperforms state-of-the-art work of tabu search and is competitive with other methods for HW/SW partitioning.The proposed parallelization is significant when considering the ordinary GPU platform.

New Model and Algorithm for Hardware/Software Partitioning

This paper focuses on the algorithmic aspects for the hardware/software （HW/SW） partitioning which searches a reasonable composition of hardware and software components which not only satisfies the constraint of hardware area but also optimizes the execution time. The computational model is extended so that all possible types of communications can be taken into account for the HW/SW partitioning. Also, a new dynamic programming algorithm is proposed on the basis of the computational model, in which source data, rather than speedup in previous work, of basic scheduling blocks are directly utilized to calculate the optimal solution. The proposed algorithm runs in O（n·A） for n code fragments and the available hardware area A. Simulation results show that the proposed algorithm solves the HW/SW partitioning without increase in running time, compared with the algorithm cited in the literature.

Convergence Platform of Cloud Computing and Internet of Things (IoT) for Smart Healthcare Application

Internet of Things (IoT) is a widely distributed network which requires small amount of power supply having limited storage and processing capacity. On the other hand, Cloud computing has virtually unlimited storage and processing capabilities and is a much more mature technology. Therefore, combination of Cloud computing and IoT can provide the best performance for users. Cloud computing nowadays provides lifesaving healthcare application by collecting data from bedside devices, viewing patient information and diagnose in real time. There may some concerns about security and other issues of the patient’s data but utilization of IoT and Cloud technologies in healthcare industry would open a new era in the field of healthcare. To ensure basic healthcare needs of the people in the rural areas, we have proposed Cloud-IoT based smart healthcare system. In this system various types of sensors (Temperature, Heart bit, ECG, etc.) are equipped in the patient side to sense the patient’s physiological data. For securing data RSA based authentication algorithm and mitigation of several security threats have been used. The sensed data will process and store in the Cloud server. Stored data can be used by the authorized and/or concerned medical practitioner upon approved by the user for patient caring.

A HW/SW Co-Verification Technique for FPGA Test

Field programmable gate arrays （FPGAs） have wide and extensive applications in many areas. Due to programmable feature of FPGAs, faults of FPGAs can be easily tolerated if fault sites can be located. A hardware/software （HW/SW） co-verification technique for FPGA test is proposed in this paper. Taking advantage of flexibility and observability of software in conjunction with high-speed simulation of hardware, this technique is capable of testing each input/output block （IOB） and configurable logic block （CLB） of FPGA automatically, exhaustively and repeatedly. Fault cells of FPGA can be positioned automatically by the proposed approach. As a result, test efficiency and reliability can be enhanced without manual work.

Brain-inspired Intelligent Robotics:Theoretical Analysis and Systematic Application

Traditional joint-link robots have been widely used in production lines because of their high precision for single tasks.With the development of the manufacturing and service industries,the requirement for the comprehensive performance of robotics is growing.Numerous types of bio-inspired robotics have been investigated to realize human-like motion control and manipulation.A study route from inner mechanisms to external structures is proposed to imitate humans and animals better.With this idea,a brain-inspired intelligent robotic system is constructed that contains visual cognition,decision-making,motion control,and musculoskeletal structures.This paper reviews cutting-edge research in brain-inspired visual cognition,decision-making,motion control,and musculoskeletal systems.Two software systems and a corresponding hardware system are established,aiming at the verification and applications of next-generationbrain-inspired musculoskeletal robots.

SoftSSD:enabling rapid flash firmware prototyping for solid-state drives

Recently,solid-state drives(SSDs)have been used in a wide range of emerging data processing systems.Essentially,an SSD is a complex embedded system that involves both hardware and software design.For the latter,firmware modules such as the flash translation layer(FTL)orchestrate internal operations and flash management,and are crucial to the overall input/output performance of an SSD.Despite the rapid development of new SSD features in the market,the research of flash firmware has been mostly based on simulations due to the lack of a realistic and extensible SSD development platform.In this paper,we propose SoftSSD,a software-oriented SSD development platform for rapid flash firmware prototyping.The core of SoftSSD is a novel framework with an event-driven programming model.With the programming model,new FTL algorithms can be implemented and integrated into a full-featured flash firmware in a straightforward way.The resulting flash firmware can be deployed and evaluated on a hardware development board,which can be connected to a host system via peripheral component interconnect express and serve as a normal non-volatile memory express SSD.Different from existing hardware-oriented development platforms,SoftSSD implements the majority of SSD components(e.g.,host interface controller)in software,so that data flows and internal states that were once confined in the hardware can now be examined with a software debugger,providing the observability and extensibility that are critical to the rapid prototyping and research of flash firmware.We describe the programming model and hardware design of SoftSSD.We also perform experiments with real application workloads on a prototype board to demonstrate the performance and usefulness of SoftSSD,and release the open-source code of SoftSSD for public access.

Key technologies of system on chip design

The most supreme characteristic of SoC （system on chip） era is the high complexity of the chips; architecture and software design have become the indivisible part of chip design. As semiconductor fabrication technology evolves into very deep sub-micron （DSM） level, power consumption has become the inevitable challenge in SoC design. In order to maximize the lifetime of portable system battery, SoC is required not only to be energy-efficient but also to work in an optimal and battery-aware manner. This paper intends to discuss some key technologies of SoC design from the above perspectives of view.

Towards“General Purpose”Brain-Inspired Computing System

Brain-inspired computing refers to computational models,methods,and systems,that are mainly inspired by the processing mode or structure of brain.A recent study proposed the concept of"neuromorphic completeness"and the corresponding system hierarchy,which is helpful to determine the capability boundary of brain-inspired computing system and to judge whether hardware and software of brain-inspired computing are compatible with each other.As a position paper,this article analyzes the existing brain-inspired chips design characteristics and the current so-called"general purpose"application development frameworks for brain-inspired computing,as well as introduces the background and the potential of this proposal.Further,some key features of this concept are presented through the comparison with the Turing completeness and approximate computation,and the analyses of the relationship with"general-purpose"brain-inspired computing systems(it means that computing systems can support all computable applications).In the end,a promising technical approach to realize such computing systems is introduced,as well as the on-going research and the work foundation.We believe that this work is conducive to the design of extensible neuromorphic complete hardware-primitives and the corresponding chips.On this basis,it is expected to gradually realize"general purpose"brain-inspired computing system,in order to take into account the functionality completeness and application efficiency.

Power optimization and performance improvement for embedded Ethernet SOC

Information appliance is the combination of traditional home appliances and the internet technology. In this article, an Ethernet controller system-on-chip （SOC） solution for information appliances is presented. To achieve high performance, the embedded 8 bits 8051 micro control unit （MCU） is optimized by an independent instruction bus and a data bus. Besides, a two-stage pipeline feature is added. Compared with the existing 8051 core, the enhanced one-cycle MCU offers ten times improvement in instruction execution efficiency. Meanwhile, the performance of media access control （MAC） circuit is greatly improved by adopting various techniques such as direct memory access （DMA） control, paging strategy, etc. To reduce the power consumption, clock gating, low power supply, and multi-working-clock are adopted. Moreover, to achieve rapid data communication in different clock frequency circuits, a simple ping-pong first in first out （FIFO） circuit is realized. The chip is implemented using TSMC 0.25 μm two-poly four-metal mixed signal complementary metal oxide semiconductor （CMOS） technology. Its die area is 4.8 min× 4.6 mm. The test results show that the maximum throughput of Ethernet packets can reach 7 Mb/s while the power consumption is rather low-the working current is just about 200 mA.

HW/SW Co-optimization for Stencil Computation：Beginning with a Customizable Core

Energy efficiency is one of the most important issues for High Performance Computing（HPC） today.Heterogeneous HPC platform with some energy-efficient customizable cores（as application-specific accelerators）is believed as one of the promising solutions to meet ever-increasing computing needs and to overcome power density limitations. In this paper, we focus on using customizable processor cores to optimize the typical stencil computations—— the kernel of many high-performance applications. We develop a series of effective software/hardware co-optimization strategies to exploit the instruction-level and memory-computation parallelism,as well as to decrease the energy consumption. These optimizations include loop tiling, prefetching, cache customization, Single Instruction Multiple Data（SIMD）, and Direct Memory Access（DMA）, as well as necessary ISA extensions. Detailed tests of power-efficiency are given to evaluate the effect of all these optimizations comprehensively. The results are impressive： the combination of these optimizations has improved the application performance by 341% while the energy consumption has been decreased by 35%; a preliminary comparison with X86, GPU, and FPGA platforms also showed that the design could achieve an order of magnitude higher performance efficiency. We believe this work can help understand sources of inefficiency in general-purpose chips and can be used as a beginning to customize an energy efficient CMP for further improvement.