As the technology of IP-core-reused has been widely used, a lot of intellectual property (IP) cores have been embedded in different layers of system-on-chip (SOC). Although the cycles of development and overhead a...As the technology of IP-core-reused has been widely used, a lot of intellectual property (IP) cores have been embedded in different layers of system-on-chip (SOC). Although the cycles of development and overhead are reduced by this method, it is a challenge to the SOC test. This paper proposes a scheduling method based on the virtual flattened architecture for hierarchical SOC, which breaks the hierarchical architecture to the virtual flattened one. Moreover, this method has more advantages compared with the traditional one, which tests the parent cores and child cores separately. Finally, the method is verified by the ITC'02 benchmark, and gives good results that reduce the test time and overhead effectively.展开更多
基金Project supported by the Applied Materials Foundation Project of Science and Technology Commission of Shanghai Mu-nicipality (Grant No.08700741000)the System Design on Chip Project of Science and Technology Commission of Shanghai Municipality (Grant No.08706201000)+1 种基金the Leading Academic Discipline Project of Shanghai Municipal Education Committee(Grant No.J50104)the Innovation Foundation Project of Shanghai University
文摘As the technology of IP-core-reused has been widely used, a lot of intellectual property (IP) cores have been embedded in different layers of system-on-chip (SOC). Although the cycles of development and overhead are reduced by this method, it is a challenge to the SOC test. This paper proposes a scheduling method based on the virtual flattened architecture for hierarchical SOC, which breaks the hierarchical architecture to the virtual flattened one. Moreover, this method has more advantages compared with the traditional one, which tests the parent cores and child cores separately. Finally, the method is verified by the ITC'02 benchmark, and gives good results that reduce the test time and overhead effectively.