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Scheduling method based on virtual flattened architecture for Hierarchical system-on-chip
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作者 张冬 张金艺 +1 位作者 杨晓冬 杨毅 《Journal of Shanghai University(English Edition)》 CAS 2009年第6期433-437,共5页
As the technology of IP-core-reused has been widely used, a lot of intellectual property (IP) cores have been embedded in different layers of system-on-chip (SOC). Although the cycles of development and overhead a... As the technology of IP-core-reused has been widely used, a lot of intellectual property (IP) cores have been embedded in different layers of system-on-chip (SOC). Although the cycles of development and overhead are reduced by this method, it is a challenge to the SOC test. This paper proposes a scheduling method based on the virtual flattened architecture for hierarchical SOC, which breaks the hierarchical architecture to the virtual flattened one. Moreover, this method has more advantages compared with the traditional one, which tests the parent cores and child cores separately. Finally, the method is verified by the ITC'02 benchmark, and gives good results that reduce the test time and overhead effectively. 展开更多
关键词 system-on-chip test virtual flat hierarchical SOC test scheduling
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