Design and implementation of 1 GHz high speed data acquisition system

With the development of current electronic technology, numerous high-speed data acquisition systems provide a variety of potential benefits. This article describes a high-speed data acquisition system which consists of ECL logic and TTL logic devices, samples and stores data with a 1 GHz clock. This system is accomplished easily and works stably. A performance test of this system has been undertaken and the results show that the effective number of bits （ENOB） is more than 6.5 bits.

High-speed broadband data acquisition system based on FPGA

A field-programmable gate array(FPGA)based high-speed broadband data acquisition system is designed.The system has a dual channel simultaneous acquisition function.The maximum sampling rate is 500 MSa/s and bandwidth is200 MHz,which solves the large bandwidth,high-speed signal acquisition and processing problems.At present,the data acquisition system is successfully used in broadband receiver test systems.

A Storage Architecture for High Speed Signal Processing: Embedding RAID 0 on FPGA

The article proposes a new architecture based on RAID 0 tech in computer science for signal processing field to store high speed data. It is composed of SSD driven by FPGA, called SSD-based RAID on FPGA. This new architecture features high storage rate, mass capacity and small volume, and it is an efficient solution to store high speed data. The article describes the construction of SRF in details, and shows the test result of a demo system based on the architecture.

Analysis and Impact of Surface Acoustic Wave Filter in-Band Ripple on Testing and Measurement of High Data Rate Communications

In this paper, we present a background and theory of the effect of Surface Acoustic Wave (SAW) Filter Module (SFM) in-band ripple on high data rate communications parameters such as the Error Vector Magnitude (EVM). In addition, we present analyses and statements for the choice of unbalanced S-parameters set of the SFM over balanced S-parameters set of the SFM in measurements and Agilent’s Advance Design System (ADS) Ptolemy simulations. A test and measurement setup using Agilent’s equipment will be presented.

An Optimal Feed Interpolator Based on G^2 Continuous Bézier Curves for High-Speed Machining of Linear Tool Path

A numerical control (NC) tool path of digital CAD model is widely generated as a set of short line segments in machining. However, there are three shortcomings in the linear tool path, such as discontinuities of tangency and curvature, huge number of line segments, and short lengths of line segments. These disadvantages hinder the development of high speed machining. To smooth the linear tool path and improve machining efficiency of short line segments, this paper presents an optimal feed interpolator based on G^2 continuous Bézier curves for the linear tool path. First, the areas suitable for fitting are screened out based on the geometric characteristics of continuous short segments (CSSs). CSSs in every area are compressed and fitted into a G^2 Continuous Bézier curve by using the least square method. Then a series of cubic Bézier curves are generated. However, the junction between adjacent Bézier curves is only G^0 continuous. By adjusting the control points and inserting Bézier transition curves between adjacent Bézier curves, the G^2 continuous tool path is constructed. The fitting error is estimated by the second-order Taylor formula. Without iteration, the fitting algorithm can be implemented in real-time environment. Second, the optimal feed interpolator considering the comprehensive constraints (such as the chord error constraint, the maximum normal acceleration, servo capacity of each axis, etc.) is proposed. Simulation and experiment are conducted. The results shows that the proposed method can generate smooth path, decrease the amount of segments and reduce machining time for machining of linear tool path. The proposed research provides an effective method for high-speed machining of complex 2-D/3-D profiles described by short line segments.

A fault prediction method for catenary of high-speed rails based on meteorological conditions

Fault frequency of catenary is related to meteo-rological conditions. In this work, based on the historical data, catenary fault frequency and weather-related fault rate are introduced to analyse the correlation between catenary faults and meteorological conditions, and further the effect of meteorological conditions on catenary oper-ation. Moreover, machine learning is used for catenary fault prediction. As with the single decision tree, only a small number of training samples can be classified cor-rectly by each weak classifier, the AdaBoost algorithm is adopted to adjust the weights of misclassified samples and weak classifiers, and train multiple weak classifiers. Finally, the weak classifiers are combined to construct a strong classifier, with which the final prediction result is obtained. In order to validate the prediction method, an example is provided based on the historical data from a railway bureau of China. The result shows that the mapping relation between meteorological conditions and catenary faults can be established accurately by AdaBoost algorithm. The AdaBoost algorithm can accurately predict a catenary fault if the meteorological conditions are provided.

Statistical delay distribution analysis on high-speed railway trains

The focus of this study is to explore the statis-tical distribution models of high-speed railway (HSR) train delays. Based on actual HSR operational data, the delay causes and their classification, delay frequency, number of affected trains, and space–time delay distributions are discussed. Eleven types of delay events are classified, and a detailed analysis of delay distribution for each classifica-tion is presented. Models of delay probability delay prob-ability distribution for each cause are proposed. Different distribution functions, including the lognormal, exponen-tial, gamma, uniform, logistic, and normal distribution, were selected to estimate and model delay patterns. The most appropriate distribution, which can approximate the delay duration corresponding to each cause, is derived. Subsequently, the Kolmogorov–Smirnov (K–S) test was used to test the goodness of fit of different train delay distribution models and the associated parameter values. The test results show that the distribution of the test data is consistent with that of the selected models. The fitting distribution models show the execution effect of the timetable and help in finding out the potential conflicts in real-time train operations.

基于FPGA的高速Aurora接口通信系统设计

在通信领域和电子工业应用中板级间的高速传输接口设计一直扮演着重要的角色,基于在工程实践中经常要解决高速串行数据传输的问题,设计了一种基于FPGA的实用高速接口通信系统。系统采用Xilinx公司的Kin-tex-7系列芯片,提出一种基于Aurora 64b/66b IP核的高速数据传输方法,详细介绍了Aurora 64b/66b IP核的结构与功能,实现了Aurora 64b/66b IP核的四路10G高速通信,系统通信速率可达40Gbps,并进行了高速接口传输模块设计和连通性功能仿真。

基于FPGA的多通道高速串行数据采集系统设计

针对卫星导航信号抗干扰领域中进行高精度高速多通道数据采集的需要,系统采用ADI公司的16位高速串行AD转换芯片AD9653,完成模数转换,其转换精度可达16比特,转换速率最高为125MSPS。分析AD9653的高速串行数据接口特点,采用Xilinx公司的Kintex-7系列FPGA提供的片同步技术,进行位时钟自适应相位校准和数据帧调整研究,保证了高速串行数据传输的稳定性与正确性。采用内部FIFO数据缓存的方式实现多通道数据的片内同步以保证后续抗干扰算法的正确处理。研究结果表明,使用该方法进行高速串行数据采集时系统稳定可靠、正确无误。为多通道高速串行数据采集提供了一种切实可行的解决方案,对类似需求的数据采集系统具有一定的参考价值。

高铁场景下意图驱动的网络智能运营研究

随着4G/5G网络的深入应用,高铁移动网络的用网体验成为人们持续关注的焦点。对高铁场景下意图驱动的网络智能运营进行了研究。充分利用大数据和AI技术等新质生产力技术,采用高铁车体移动指纹分析、切换序列判定等算法精准识别高铁用户,采用时序覆盖特征分析、频繁项挖掘算法等技术准确识别高铁路网覆盖情况,并以此为基础构建出高铁质差用户和小区的“评估-定位-闭环处理-效果验证”端到端闭环处理流程。

数字示波器中FPGA间高速信号传输同步方法

数据采集系统是数字示波器(DSO)的核心组成单元,随着示波器带宽采样率的逐步提升,单片模数转换器(ADC)+现场可编辑门控阵列(FPGA)的架构难以满足超高速以及多通道的应用场景,因此,高端示波器中数据采集系统普遍采用“主从”FPGA控制架构。在该架构下,多个FPGA之间信号的同步传输是实现采集系统的同步和精确采集的重要前提。针对多FPGA板卡之间的信号同步传输问题,提出了一种FPGA之间高速信号同步传输的方法,借助FPGA的IODELAY单元,通过测试数据训练找到最稳定的同步传输区间,实现多FPGA之间的同步传输。在自研的数字示波器上的实验表明,该方法能够有效实现FPGA之间高速信号的同步传输。

多GPU系统的高速互联技术与拓扑发展现状研究

多GPU系统通过横向扩展实现性能提升,以满足人工智能日趋复杂的算法和持续激增的数据所带来的不断增长的计算需求。对于多GPU系统而言,处理器间的互联带宽以及系统的拓扑是决定系统性能的关键因素。在传统的基于PCIe的多GPU系统中,PCIe带宽是限制系统性能的瓶颈。当前,面向GPU的高速互联技术成为解决多GPU系统带宽限制问题的有效方法。本文首先介绍了传统多GPU系统所采用的PCIe互联技术及其典型拓扑,然后以Nvidia NVLink、AMD Infinity Fabric Link、Intel X^(e) Link、壁仞科技BLink为例,对国内外代表性GPU厂商的面向GPU的高速互联技术及其拓扑进行了梳理分析,最后讨论了关于互联技术的研究启示。

指控中心任务软件集中管控系统研究与关键技术

随着武器航天试验任务的增多,指控中心对任务软件快速部署、多任务并行的需求愈发迫切。设计了基于B/S架构的指控中心任务软件集中管控系统,实现了任务软件配置与监控的一体化管理;通过基于DBus与Kafka结合的数据传输机制,打通了任务软件与系统前后端数据高效交互链路;最后,重点分析了任务软件自动化部署技术、多任务并行技术、高速数据分级处理技术以及任务数据高效存储技术。

高速铁路动检车轴箱加速度与轮轨力数据里程对齐研究

高速铁路动检数据对轨道养护维修具有重要意义,其中轴箱加速度和轮轨力是两种能够反映轨道短波不平顺信息且相互关联的高频采样数据。然而,这两种数据之间存在里程误差,以至于在评价轨道平顺性时无法建立参考基准。现有的动检数据里程修正方法大多需要结合线路台账信息,主要针对轨道几何不平顺数据的里程对齐,鲜有适用于无线路超高信息且高频采样下的轴箱加速度和轮轨力里程对齐方法。提出一种二阶段窗长收敛的里程误差修正模型,结合线性插值方法调整全局波形。根据某高速铁路实测轴箱加速度、轮轨力数据修正结果表明:该线路区间的里程误差在第一阶段修正后从1 km左右减小至42 m以内,经第二阶段精确修正后误差在99.7%的置信度下可控制在1.55 m以内。数据能量趋势结果表明,修正后轴箱加速度、轮轨力数据趋势线性相关性在全区段显著提升。

高速铁路动静态轨检数据里程对齐与误差修正

轨道几何动、静检测数据间的精确匹配对探明高速铁路线路服役状态和制定准确可靠的养护维修策略具有关键作用。针对动静里程匹配算法研究较少的现状,提出利用动、静态实测数据波形匹配,建立基于互相关函数与动态时间规划相结合的两阶段修正算法,并以距离误差作为评价指标。结合某高铁线路轨道几何检测数据的案例分析,以静态检测数据作为参考基准,对动态检测数据进行里程误差评估与修正。结果表明,两阶段算法修正效果显著,累积距离误差降幅超过93%,修正后的动、静态检测数据严格对齐保证了动态检测数据的可靠性与有效性。

基于FPGA的雷达/GPS数据融合存储系统设计

现阶段高速测绘成像雷达回波信号数据量大、传输速率快,完整的实时存储高精度GPS信息的雷达数据是测绘成像的关键,面对此类系统要求满足高精度、数据融合编帧、大容量、高速度、全程准确存储等一系列问题,该文设计一种高速雷达融合数据接口控制存储系统。该系统主控模块以FPGA作为主控芯片,接收10路30 MB/s的LVDS数据和1路GPS串口数据,并进行组合编帧,打包数据通过以太网发送给上位机,最后通过LabView上位机软件将数据存储在硬盘内。最终通过试验验证,可以完整无误地将融合采编数据存储在硬盘内。

无砟轨道区段维修时间识别与劣化速率分析

针对运营前期信息化程度不足导致的高速铁路线路历史维修记录缺失进而影响后期高速铁路运维合理规划的问题,建立基于信息熵和数值滤波的高速铁路高低不平顺维修时间识别模型.首先,基于挖掘长时间跨度下的轨道动检数据,获取精确的维修信息并揭示线路维修与不平顺劣化速度的关系.然后,将模型提取时间节点与某CRTSΙ型板式无砟轨道的综合检测列车历史维修数据对比,分析模型提取效果.最后,采用线性回归进行不同劣化时间段劣化速率预测和分析.结果表明:维修作业方案的改善程度不同,18%的维修方案能够实现高低不平顺原始数据70%的改善量,75%的维修方案能够实现高低不平顺原始数据30%的改善量;对比不同轨下结构类型,劣化速率最大的10%个线路区段所需平均维修周期隧道段最长,为28个月,桥梁段最短,为9个月;未开展维修的线路区段占整体线路的18%,高低不平顺标准差劣化速率分布较为集中,不超过0.01 mm/月;自2016年1月起,依靠日常检养修工作,预计下次维修时间最早为82个月后.

FPGA高速数据采集的WEDM在线脉冲识别

为了提高电火花加工放电间隙的实时识别准确率,文中提出了一种基于FPGA高速数据采集的神经网络的放电间隙在线识别方案。利用FPGA和AD模块对加工间隙电压数据进行高速采集,通过FPGA内部的FIFO和串口协同实现周期性数据传输。在Python的Pytorch库构建了CNN GRU融合神经网络模型,对所采集的数据进行在线识别,验证了该采集系统的可行性。实验结果表明:文中方案对加工电压脉冲的离线识别准确率达到了97.35%,优于CNN和GRU方法,满足了电火花加工对间隙电压识别的高精度要求,实现了神经网络的实时在线识别放电间隙。