Aim at improving the stability of the Short-circuiting Gas Metal Arc Welding （GMAW-S） process for the enhanced speed usage, effects of current waveform parameters during short-term on the welding stability have been...Aim at improving the stability of the Short-circuiting Gas Metal Arc Welding （GMAW-S） process for the enhanced speed usage, effects of current waveform parameters during short-term on the welding stability have been investigated by experimental method. The welding power source used for the research is an inverter with a special current waveform control. It is shown that the spatter decreases at first then increases with each increase of the low current period, current increase rate and the maximum current limit. The test results are provided for welding of 1 mm and 3 mm mild steel at speed of 1.2 m/min. The stable GMA W-S process under high speed welding condition has been achieved by optimizing the parameters.展开更多
A new method for analyzing high-speed circuit systems is presented. The method adds transmission line end currents to the circuit variables of the classical modified nodal approach. Then the matrix equation describing...A new method for analyzing high-speed circuit systems is presented. The method adds transmission line end currents to the circuit variables of the classical modified nodal approach. Then the matrix equation describing high-speed circuit system can be formulated directly and analyzed conveniently for its normative form. A time-domain analysis method for transmission lines is also introduced. The two methods are combined together to efficiently analyze high-speed circuit systems having general transmission lines. Numerical experiment is presented and the results are compared with that calculated by Hspice.展开更多
Analysis approach and formulas for the transmission properties of uniform multicon-ductor interconnecting buses in high-speed integrated circuits are presented in this article. And further, by using a network approach...Analysis approach and formulas for the transmission properties of uniform multicon-ductor interconnecting buses in high-speed integrated circuits are presented in this article. And further, by using a network approach, a tapered bus system can be analyzed as a set of cascaded uniform buses with slightly different strip widths. Obtained results are in good agreement with the experimental data.展开更多
This paper presents an analysis method, based on MacCormack＇s technique, for the evaluation of the time domain sensitivity of distributed parameter elements in high-speed circuit networks. Sensitivities can be calcul...This paper presents an analysis method, based on MacCormack＇s technique, for the evaluation of the time domain sensitivity of distributed parameter elements in high-speed circuit networks. Sensitivities can be calculated from electrical and physical parameters of the distributed parameter elements. The proposed method is a direct numerical method of time-space discretization and does not require complicated mathematical deductive process. Therefore, it is very convenient to program this method. It can be applied to sensitivity analysis of general transmission lines in linear or nonlinear circuit networks. The proposed method is second-order-accurate. Numerical experiment is presented to demonstrate its accuracy and efficiency.展开更多
The paper reveals the relation between the linear AND-OR gate and the emitter function logic. With theoretic calculation and PSPICE simulation, the paper proves that the linear AND-OR gates can work at super-high-spee...The paper reveals the relation between the linear AND-OR gate and the emitter function logic. With theoretic calculation and PSPICE simulation, the paper proves that the linear AND-OR gates can work at super-high-speed and can be multi-cascaded. On the basis of analyzing the high-speed switch units which coordinate with linear AND-OR gates, two kinds of emitter coupled logic circuits are designed. The paper also discusses the design principles of super-high-speed digital circuits, and some examples of combinational and sequential circuits using linear AND-OR gate are given.展开更多
This paper presents a method based on a sample-decision(SD) circuit to suppress crosstalk and noise for a high-speed and high-density bus system.A method to count the number of times of SD for different length of tran...This paper presents a method based on a sample-decision(SD) circuit to suppress crosstalk and noise for a high-speed and high-density bus system.A method to count the number of times of SD for different length of transmission lines is presented and a bit error rates(BERs) formula is given by the SD circuit.It is shown that for long transmission line systems,multiple SD circuits can improve the BERs significantly.Circuits simulation for single SD method is also done,it is found that when the amplitude peak values of the superposed crosstalk and noise are less than half of the corresponding signal ones,they will be eliminated completely for the cases investigated.展开更多
As technology shrinks in modern era the demand on high speed, low power consumption and small chip area in microprocessors is come into existence. In this paper we have presented a new class of domino circuit design f...As technology shrinks in modern era the demand on high speed, low power consumption and small chip area in microprocessors is come into existence. In this paper we have presented a new class of domino circuit design for low power consumption, faster circuit speed and high performance. Due to wide fan-in domino logic, its logic gate suffer from noise sensitivity, if we improve sensitivity, sub-threshold and gate oxide leakage current dominate in evaluation network, which increases the power consumption and reduces the performance of the circuit. The proposed circuit improves the dynamic power consumption and reduces the delay which improves the speed of the circuit. Simulation is performed in BISM4 Cadence environment at 65 nm process technology, with supply voltage 1 V at 100 MHz frequency and bottleneck operating temperature of 27°C with CL = 1 fF. From the result average power improvement by proposed circuit 1 & 2 for 8 input OR gate is 10.1%, 15.28% SFLD, 48.56%, 51.49% CKD, 55.17%, 57.71% HSD and improvement of delay is 1.10%, 12.76% SFLD, 19.13%, 28.63% CKD, 4.32%, 15.59% HSD, 19.138%, 44.25% DFD respectively.展开更多
文摘Aim at improving the stability of the Short-circuiting Gas Metal Arc Welding （GMAW-S） process for the enhanced speed usage, effects of current waveform parameters during short-term on the welding stability have been investigated by experimental method. The welding power source used for the research is an inverter with a special current waveform control. It is shown that the spatter decreases at first then increases with each increase of the low current period, current increase rate and the maximum current limit. The test results are provided for welding of 1 mm and 3 mm mild steel at speed of 1.2 m/min. The stable GMA W-S process under high speed welding condition has been achieved by optimizing the parameters.
文摘A new method for analyzing high-speed circuit systems is presented. The method adds transmission line end currents to the circuit variables of the classical modified nodal approach. Then the matrix equation describing high-speed circuit system can be formulated directly and analyzed conveniently for its normative form. A time-domain analysis method for transmission lines is also introduced. The two methods are combined together to efficiently analyze high-speed circuit systems having general transmission lines. Numerical experiment is presented and the results are compared with that calculated by Hspice.
文摘Analysis approach and formulas for the transmission properties of uniform multicon-ductor interconnecting buses in high-speed integrated circuits are presented in this article. And further, by using a network approach, a tapered bus system can be analyzed as a set of cascaded uniform buses with slightly different strip widths. Obtained results are in good agreement with the experimental data.
文摘This paper presents an analysis method, based on MacCormack＇s technique, for the evaluation of the time domain sensitivity of distributed parameter elements in high-speed circuit networks. Sensitivities can be calculated from electrical and physical parameters of the distributed parameter elements. The proposed method is a direct numerical method of time-space discretization and does not require complicated mathematical deductive process. Therefore, it is very convenient to program this method. It can be applied to sensitivity analysis of general transmission lines in linear or nonlinear circuit networks. The proposed method is second-order-accurate. Numerical experiment is presented to demonstrate its accuracy and efficiency.
基金Supported by the National Natural Science Foundation of China
文摘The paper reveals the relation between the linear AND-OR gate and the emitter function logic. With theoretic calculation and PSPICE simulation, the paper proves that the linear AND-OR gates can work at super-high-speed and can be multi-cascaded. On the basis of analyzing the high-speed switch units which coordinate with linear AND-OR gates, two kinds of emitter coupled logic circuits are designed. The paper also discusses the design principles of super-high-speed digital circuits, and some examples of combinational and sequential circuits using linear AND-OR gate are given.
基金Supported by the National Natural Science Foundation of China(No.61171039,61072059)
文摘This paper presents a method based on a sample-decision(SD) circuit to suppress crosstalk and noise for a high-speed and high-density bus system.A method to count the number of times of SD for different length of transmission lines is presented and a bit error rates(BERs) formula is given by the SD circuit.It is shown that for long transmission line systems,multiple SD circuits can improve the BERs significantly.Circuits simulation for single SD method is also done,it is found that when the amplitude peak values of the superposed crosstalk and noise are less than half of the corresponding signal ones,they will be eliminated completely for the cases investigated.
文摘As technology shrinks in modern era the demand on high speed, low power consumption and small chip area in microprocessors is come into existence. In this paper we have presented a new class of domino circuit design for low power consumption, faster circuit speed and high performance. Due to wide fan-in domino logic, its logic gate suffer from noise sensitivity, if we improve sensitivity, sub-threshold and gate oxide leakage current dominate in evaluation network, which increases the power consumption and reduces the performance of the circuit. The proposed circuit improves the dynamic power consumption and reduces the delay which improves the speed of the circuit. Simulation is performed in BISM4 Cadence environment at 65 nm process technology, with supply voltage 1 V at 100 MHz frequency and bottleneck operating temperature of 27°C with CL = 1 fF. From the result average power improvement by proposed circuit 1 & 2 for 8 input OR gate is 10.1%, 15.28% SFLD, 48.56%, 51.49% CKD, 55.17%, 57.71% HSD and improvement of delay is 1.10%, 12.76% SFLD, 19.13%, 28.63% CKD, 4.32%, 15.59% HSD, 19.138%, 44.25% DFD respectively.
