Damage effects and mechanism of the silicon NPN monolithic composite transistor induced by high-power microwaves

A two-dimensional model of the silicon NPN monolithic composite transistor is established for the first time by utilizing the semiconductor device simulator, Sentaurus-TCAD. By analyzing the internal distributions of electric field, current density, and temperature of the device, a detailed investigation on the damage process and mechanism induced by high-power microwaves （HPM） is performed. The results indicate that the temperature elevation occurs in the negative half-period and the temperature drop process is in the positive half-period under the HPM injection from the output port. The damage point is located near the edge of the base-emitter junction of T2, while with the input injection it exists between the base and the emitter of T2. Comparing these two kinds of injection, the input injection is more likely to damage the device than the output injection. The dependences of the damage energy threshold and the damage power threshold causing the device failure on the pulse-width are obtained, and the formulas obtained have the same form as the experimental equations, which demonstrates that more power is required to destroy the device if the pulse-width is shorter. Furthermore, the simulation result in this paper has a good coincidence with the experimental result.

Designing power heterojunction bipolar transistors with non-uniform emitter finger lengths to achieve high thermal stability

With the aid of a thermal-electrical model, a practical method for designing multi-finger power heterojunction bipolar transistors with finger lengths divided in groups is proposed. The method can effectively enhance the thermal stability of the devices without sacrificing the design time. Taking a 40-finger heterojunction bipolar transistor for example, the device with non-uniform emitter finger lengths is optimized and fabricated. Both the theoretical and the experimental results show that, for the optimum device, the peak temperature is lowered by 26.19 K and the maximum temperature difference is reduced by 56.67% when compared with the conventional heterojunction bipolar transistor with uniform emitter finger length. Furthermore, the ability to improve the uniformity of the temperature profile and to expand the thermal stable operation range is strengthened as the power level increases, which is ascribed to the improvement of the thermal resistance in the optimum device. A detailed design procedure is also summarized to provide a general guide for designing power heterojunction bipolar transistors with non-uniform finger lengths.

Microwave damage susceptibility trend of a bipolar transistor as a function of frequency

We conduct a theoretical study of the damage susceptibility trend of a typical bipolar transistor induced by a high-power microwave （HPM） as a function of frequency. The dependences of the burnout time and the damage power on the signal frequency are obtained. Studies of the internal damage process and the mechanism of the device are carried out from the variation analysis of the distribution of the electric field, current density, and temperature. The investigation shows that the burnout time linearly depends on the signal frequency. The current density and the electric field at the damage position decrease with increasing frequency. Meanwhile, the temperature elevation occurs in the area between the p-n junction and the n n＋ interface due to the increase of the electric field. Adopting the data analysis software, the relationship between the damage power and frequency is obtained. Moreover, the thickness of the substrate has a significant effect on the burnout time.

Hardening measures for bipolar transistors against microwave-induced damage

In the present paper we study the influences of the bias voltage and the external components on the damage progress of a bipolar transistor induced by high-power microwaves. The mechanism is presented by analyzing the variation in the internal distribution of the temperature in the device. The findings show that the device becomes less vulnerable to damage with an increase in bias voltage. Both the series diode at the base and the relatively low series resistance at the emitter, Re, can obviously prolong the burnout time of the device. However, Re will aid damage to the device when the value is sufficiently high due to the fact that the highest hot spot shifts from the base-emitter junction to the base region. Moreover, the series resistance at the base Rb will weaken the capability of the device to withstand microwave damage.

Effects of microwave pulse-width damage on a bipolar transistor

This paper presents a theoretical study of the pulse-width effects on the damage process of a typical bipolar transistor caused by high power microwaves（HPMs） through the injection approach.The dependences of the microwave damage power,P,and the absorbed energy,E,required to cause the device failure on the pulse width τ are obtained in the nanosecond region by utilizing the curve fitting method.A comparison of the microwave pulse damage data and the existing dc pulse damage data for the same transistor is carried out.By means of a two-dimensional simulator,ISE-TCAD,the internal damage processes of the device caused by microwave voltage signals and dc pulse voltage signals are analyzed comparatively.The simulation results suggest that the temperature-rising positions of the device induced by the microwaves in the negative and positive half periods are different,while only one hot spot exists under the injection of dc pulses.The results demonstrate that the microwave damage power threshold and the absorbed energy must exceed the dc pulse power threshold and the absorbed energy,respectively.The dc pulse damage data may be useful as a lower bound for microwave pulse damage data.

The pulsed microwave damage trend of a bipolar transistor as a function of pulse parameters

In the present paper we conduct a theoretical study of the thermal accumulation effect of a typical bipolar transistor caused by high power pulsed microwaves（HPMs）,and investigate the thermal accumulation effect as a function of pulse repetition frequency（PRF） and duty cycle.A study of the damage mechanism of the device is carried out from the variation analysis of the distribution of the electric field and the current density.The result shows that the accumulation temperature increases with PRF increasing and the threshold for the transistor is about 2 kHz.The response of the peak temperature induced by the injected single pulses indicates that the falling time is much longer than the rising time.Adopting the fitting method,the relationship between the peak temperature and the time during the rising edge and that between the peak temperature and the time during the falling edge are obtained.Moreover,the accumulation temperature decreases with duty cycle increasing for a certain mean power.

High-efficiency S-band harmonic tuning GaN amplifier

In this paper, we present a high-efficiency S-band gallium nitride （GaN） power amplifier （PA）. This amplifier is fabri- cated based on a self-developed GaN high-electron-mobility transistor （HEMT） with 10 mm gate width on SiC substrate. Harmonic manipulation circuits are presented in the amplifier. The matching networks consist of microstrip lines and discrete components. Open-circuited stub lines in both input and output are used to tune the 2rid harmonic wave and match the GaN HEMT to the highest efficiency condition. The developed amplifier delivers an output power of 48.5 dBm （70 W） with a power-added efficiency （PAE） of 72.2% at 2 GHz in pulse condition. When operating at 1.8-2.2 GHz （20% relative bandwidth）, the amplifier provides an output power higher than 48 dBm （,-~ 65 W）, with a PAE over 70% and a power gain above 15 dB. When operating in continuous-wave （CW） operating conditions, the amplifier gives an output power over 46 dBm （40 W） with PAE beyond 60% over the whole operation frequency range.

0.2~2.0GHz100W超宽带GaN功率放大器

设计并实现了一款基于0.25μm GaN高电子迁移率晶体管(HEMT)工艺的100 W超宽带功率放大器。基于SiC无源工艺设计了集成无源器件(IPD)输入预匹配电路芯片;设计了基于陶瓷基片的T型集成输出预匹配电路;基于建立的传输线变压器(TLT)的精确模型,设计了宽带阻抗变换器,在超宽频带内将50Ω的端口阻抗变换至约12.5Ω,再通过多节微带电路与预匹配后的GaN HEMT芯片实现阻抗匹配。最终,以较小的电路尺寸实现了功率放大器的超宽带性能指标。测试结果表明,功率放大器在0.2~2.0 GHz频带内,在漏极电压36 V、输入功率9 W、连续波的工作条件下,输出功率大于103 W,漏极效率大于50%,输入电压驻波比(VSWR)≤2.5。

Design of 35 GHz 1 Watt GaAs pHEMT Power Amplifier MMIC

By using 0.15 μm GaAs pHEMT （pseudomorphic high electron mobility transistor） technology,a design of millimeter wave power amplifier microwave monolithic integrated circuit （MMIC） is presented.With careful optimization on circuit structure,this two-stage power amplifier achieves a simulated gain of 15.5 dB with fluctuation of 1 dB from 33 GHz to 37 GHz.A simulated output power of more than 30 dBm in saturation can be drawn from 3 W DC supply with maximum power added efficiency （PAE） of 26%.Rigorous electromagnetic simulation is performed to make sure the simulation results are credible.The whole chip area is 3.99 mm2 including all bond pads.

大功率射频Si-VDMOS功率晶体管研制

介绍了大功率射频硅-垂直双扩散金属氧化物场效应晶体管(Si-VDMOS)的研制结果,采用栅分离降低反馈电容技术、多子胞降低源极电感技术等,从芯片原理着手,比较分析两种芯片结构设计对反馈电容的影响,以及两种布局引线对源极电感的影响,并研制出了百瓦级以上大功率射频Si-VDMOS功率晶体管系列产品。产品主要性能如下:在工作电压28 V及连续波下,采用8胞合成时,225 MHz输出功率达200 W以上,500 MHz输出功率达150 W以上;进一步增加子胞数量,采用12胞合成时,225 MHz输出功率达300 W以上,同时具备良好的增益及效率特性,与国外大功率射频Si-VDMOS功率晶体管的产品参数相比,达到了同类产品水平。

一种双管反激级联式高位取能电源设计

在柔性直流输电系统中,高位取能电源为模块化多电平换流器(MMC)的子模块控制电路供电。随着直流输电系统电压的提升,子模块直流侧的电压也随之升高。为使高位取能电源适应更高更宽范围的输入电压,设计了一种基于双管反激的级联式拓扑。首先,介绍双管反激电路的工作原理、电流控制模式及工作模态;其次,基于变压器初级电流中位值,重新推导变压器AP值公式,与传统AP值方法进行比较;然后,基于南澳柔性直流输电换流阀的相关参数,对电源主电路进行设计。最后,搭建了一台输入电压为350~4 000 V,输出为一路400 V、两路15 V的电源样机,通过实验结果验证了设计的有效性和分析的正确性。

BCD工艺中大电流下纵向双极晶体管的电流集边效应研究

在大电流条件下,随着电流密度的增加,发射区结电流集边效应、基区电导调制效应、基区展宽效应会随之出现。基于研究单位的BCD工艺,在集成CMOS和DMOS的基础上集成功率纵向NPN双极晶体管用于输出。设计了75μm×4μm、50μm×6μm、30μm×10μm三种不同尺寸的发射极并进行TCAD仿真研究。在发射极面积相同的情况下,发射极长宽比越小,TCAD可观察到的电流集边效应越严重,最终流片并进行测试验证,得出75μm×4μm的细长结构尺寸能够提升晶体管在大电流下的放大能力,较30μm×10μm的结构提升约11.4%。

基于Marx电路的固态高压脉冲电源设计

针对高压脉冲放电和低温等离子体应用的要求,设计了一种基于Marx电路的高重复频率的固态高压脉冲发生装置。该脉冲电源利用Marx电路电容并联充电、串联放电的原理,选取绝缘栅双极型晶体管(IGBT)作为放电开关,控制电路的模态切换。Marx主电路由84级单元组成,每级单元包含IGBT开关管、快恢复二极管和储能电容。实验结果表明,在输入电压为480 V直流电压,并且在300 Hz的频率下,该电源可以产生幅值为20 kV、脉宽为500 ns的高压脉冲,满足设计要求。

一款基于非线性模型设计的高性能GaN功率放大载片

采用南京电子器件研究所研制的0.35μm栅长、60 V高压AlGaN/GaN HEMT工艺,利用可缩放大信号模型仿真设计了一款工作在S波段的高性能功率放大载片。该功率放大载片由单个总栅宽为36.4 mm的GaN管芯采用混合集成内匹配方案设计而成,漏极工作电压为60 V,工作频带为2.7~3.5 GHz。测试结果表明,在环境温度300 K,脉宽250μs、占空比15%的脉冲测试条件下,功率放大载片在工作频带内最大饱和输出功率为354.8 W,最大功率附加效率为61%,功率增益大于14.7 dB,显示了GaN器件的高工作电压、高功率密度、宽工作频带等特性。

一种基于变压器集成的高位取能电源设计

在柔性直流输电系统中,高位取能电源为模块化多电平换流器(MMC)的子模块控制电路供电。目前普遍采用多路输入串联结构来使高位取能电源承受更高更宽范围的输入电压,因此存在电路中磁性元件过多及多路串联是否均压等问题。针对此类问题,设计了一种基于变压器集成式的双管反激拓扑。首先介绍双管反激拓扑结构及其工作模态;其次分析磁集成变压器自均压工作机理并推导磁集成变压器面积乘积(AP)计算公式;然后针对南澳柔性直流输电换流阀相关参数,对电源参数进行设计;最后搭建了一台输入电压为350~4000V的实验样机,实验结果验证了设计的有效性和分析的正确性。

6 GHz~18 GHz中功率放大器芯片的设计与实现

设计并实现了一款高性能的宽带中功率放大器芯片,该芯片采用0.25μm砷化镓赝调制掺杂异质结场效应晶体管工艺,并通过运用共源共栅电路结构,显著提升了放大器的增益水平。同时,引入负反馈技术,有效改善了增益的平坦度,极大地拓宽了放大器的工作带宽范围,使其能够覆盖从6 GHz~18 GHz的广泛频段,满足多样化的无线通信及雷达系统需求。实测数据表明,该芯片在指定频段内实现了稳定的17±0.3 dB增益,输入输出回波损耗均优于-10 dB,展现出了卓越的匹配性能。在5 V工作电压下,电流消耗仅为63 mA,且1 dB压缩点输出功率高达15 dBm,确保了在高功率输出时的稳定性与可靠性。此外,芯片设计紧凑,面积仅为1.94 mm×1.08 mm,为系统集成提供了极大的便利。

一种改善IMD3的高线性射频功率放大器

基于2μm砷化镓异质结双极型晶体管(GaAs HBT)工艺成功设计出了一款工作在2.4 GHz的高线性、高效率的射频功率放大器(RF PA)。针对非线性因素三阶交调失真(IMD3)对电路造成的影响,采用了一种两级功放电路结构,通过对两级偏置中的旁路电路进行调节,得到了两个反相可互消的三阶交调分量,有效地改善了功放非线性指标IMD3的值。对芯片进行测试,所得结果表明:在连续单音信号测试下,功放输出的1 dB压缩点功率(P1dB)为33.3 dBm,功率附加效率(PAE)为58%@33.3 dBm,增益为30.8 dB。在音距为1 MHz的双音信号测试下,三阶交调失真低于-50 dBc@20 dBm,最大三阶输出截断点(OIP3)为47 dBm@23.8 dBm。

应用于WiFi6的新型高线性度功率放大器设计

针对WiFi 6的设备需求,设计了一款工作在5.15 GHz~5.85 GHz的高线性度砷化镓异质结双极型晶体管射频功率放大器。为了保证大信号和高温下功率管静态工作点的稳定性,采用了一种新型有源自适应偏置电路。对射频功率检测电路进行了设计和改进,有效降低了射频系统的功耗。针对各次谐波分量产生的影响,对输出匹配网络进行了优化。仿真结果表明:该射频功率放大器芯片小信号增益达到了32.6 dB;在中心频率5.5 GHz时1 dB压缩点功率为30.4 dBm,功率附加效率超过27.9%;输出功率为26 dBm时,三阶交调失真低于-40 dBc。实测数据表明:小信号增益大于31.4 dB;5.5 GHz时1 dB压缩点功率为29.06 dBm;输出功率为26 dBm时,三阶交调失真低于-30 dBc。当输出功率为20 dBm时,二次三次谐波抑制到-30 dBc和-45 dBc。

非掺杂AlGaN/GaN微波功率HEMT

报道了研制的 Al Ga N / Ga N微波功率 HEMT,该器件采用以蓝宝石为衬底的非掺杂 Al Ga N/ Ga N异质结构 ,器件工艺采用了 Ti/ Al/ Ni/ Au欧姆接触和 Ni/ Au肖特基势垒接触以及 Si N介质进行器件的钝化 .研制的 2 0 0μm栅宽 T型布局 Al Ga N / Ga N HEMT在 1.8GHz,Vds=30 V时输出功率为 2 8.93d Bm,输出功率密度达到 3.9W/mm ,功率增益为 15 .5 9d B,功率附加效率 (PAE)为 4 8.3% .在 6 .2 GHz,Vds=2 5 V时该器件输出功率为 2 7.0 6 d Bm ,输出功率密度为 2 .5 W/ mm ,功率增益为 10 .2 4 d B,PAE为 35 .2 % .

直流条件下高反压大功率开关晶体管可靠性研究

集电极峰值电流(I_(CM))、集电极-发射极击穿电压(V_(CEO))、最大耗散功率(P_(CM))、直流二次击穿临界电压(V_(SB))是衡量大功率晶体管可靠性优劣的重要指标。依据实际电参数指标要求,首先利用TCAD半导体器件仿真软件完成了一款基于三重扩散工艺的双极型高反压大功率开关晶体管的结构设计,然后全面系统地分析了高阻单晶硅电阻率和器件集电区厚度对I_(CM)、V_(CEO)、P_(CM)及V_(SB)影响。仿真结果表明:由器件仿真得到的电学性能满足大功率晶体管电参数指标要求,器件结构参数的选择及工艺条件的设计较合理。增大单晶硅电阻率,虽然有利于提高集-射击穿电压和器件抗二次击穿能力,但不利于集电极峰值电流和最大耗散功率的提高。增大器件集电区厚度只对集-射击穿电压的提高有利,而对集电极峰值电流、最大耗散功率及抗二次击穿能力均产生不利的影响。