An InP optical 90°hybrid based on a×4 MMI coupler with a deep ridged waveguide is designed and fabricated.The working principle of the 90°hybrid is systematically introduced.Three-dimensional beam ropag...An InP optical 90°hybrid based on a×4 MMI coupler with a deep ridged waveguide is designed and fabricated.The working principle of the 90°hybrid is systematically introduced.Three-dimensional beam ropagation method(3D BPM)is used to optimize the structure parameters of the 90°hybrid.The designed compact structure is demonatrated to have a low excess loss less than-0.15 dB,a high common mode rejection ratio better than 40 dB,and a low relative phase deviation less than±2.5°.The designed hybrid is manufactured on a sandwitched structure deposited on an InP substrate.The measured results show that the common mode rejection ratios are larger than 20 dB in a range from 1520 nm to 1580 nm.The phase deviations are less than±5°in a range from 1545 nm to 1560 nm and less than±7°across the C band.The designed 90°optical hybrid is suitable well for realizing miniaturization,high-properties,and high bandwidth of coherent receiver.展开更多
An extremely low power voltage reference without resistors is presented for power-aware ASICs. In order to reduce the power dissipation, an Oguey current reference source is used to reduce the static current; a cascod...An extremely low power voltage reference without resistors is presented for power-aware ASICs. In order to reduce the power dissipation, an Oguey current reference source is used to reduce the static current; a cascode current mirror is used to increase the power supply rejection ratio (PSRR) and reduce the line sensitivity of the circuit. The voltage reference is fabricated in SMIC 0.18μm CMOS process. The measured results for the voltage reference demonstrate that the temperature coefficient of the voltage is 66 ppm/℃ in a range from 25 to 100 ℃. The line sensitivity is 0.9% in a supply voltage range of 1.8 to 3,3 V, and PSRR is -49 dB at 100 Hz. The power dissipation is 200 nW. The chip area is 0.01 mm2. The circuit can be used as an elementary circuit block for power-aware ASICs.展开更多
基金Project supported by the National Key Research and Development Program of China(Grant No.2016YFB0402404)the Beijing Natural Science Foundation,China(Grant No.4194093)the National Natural Science Foundation of China(Grant Nos.61635010,61674136,and 61435002).
文摘An InP optical 90°hybrid based on a×4 MMI coupler with a deep ridged waveguide is designed and fabricated.The working principle of the 90°hybrid is systematically introduced.Three-dimensional beam ropagation method(3D BPM)is used to optimize the structure parameters of the 90°hybrid.The designed compact structure is demonatrated to have a low excess loss less than-0.15 dB,a high common mode rejection ratio better than 40 dB,and a low relative phase deviation less than±2.5°.The designed hybrid is manufactured on a sandwitched structure deposited on an InP substrate.The measured results show that the common mode rejection ratios are larger than 20 dB in a range from 1520 nm to 1580 nm.The phase deviations are less than±5°in a range from 1545 nm to 1560 nm and less than±7°across the C band.The designed 90°optical hybrid is suitable well for realizing miniaturization,high-properties,and high bandwidth of coherent receiver.
基金Project supported by the National Natural Science Foundation of China(Nos.61161003,61264001,61166004)the Guangxi Natural Science Foundation(No.2013GXNSFAA019333)
文摘An extremely low power voltage reference without resistors is presented for power-aware ASICs. In order to reduce the power dissipation, an Oguey current reference source is used to reduce the static current; a cascode current mirror is used to increase the power supply rejection ratio (PSRR) and reduce the line sensitivity of the circuit. The voltage reference is fabricated in SMIC 0.18μm CMOS process. The measured results for the voltage reference demonstrate that the temperature coefficient of the voltage is 66 ppm/℃ in a range from 25 to 100 ℃. The line sensitivity is 0.9% in a supply voltage range of 1.8 to 3,3 V, and PSRR is -49 dB at 100 Hz. The power dissipation is 200 nW. The chip area is 0.01 mm2. The circuit can be used as an elementary circuit block for power-aware ASICs.