Design and implementation of 1 GHz high speed data acquisition system

With the development of current electronic technology, numerous high-speed data acquisition systems provide a variety of potential benefits. This article describes a high-speed data acquisition system which consists of ECL logic and TTL logic devices, samples and stores data with a 1 GHz clock. This system is accomplished easily and works stably. A performance test of this system has been undertaken and the results show that the effective number of bits (ENOB) is more than 6.5 bits.

High-speed broadband data acquisition system based on FPGA

A field-programmable gate array(FPGA)based high-speed broadband data acquisition system is designed.The system has a dual channel simultaneous acquisition function.The maximum sampling rate is 500 MSa/s and bandwidth is200 MHz,which solves the large bandwidth,high-speed signal acquisition and processing problems.At present,the data acquisition system is successfully used in broadband receiver test systems.

A Storage Architecture for High Speed Signal Processing: Embedding RAID 0 on FPGA

The article proposes a new architecture based on RAID 0 tech in computer science for signal processing field to store high speed data. It is composed of SSD driven by FPGA, called SSD-based RAID on FPGA. This new architecture features high storage rate, mass capacity and small volume, and it is an efficient solution to store high speed data. The article describes the construction of SRF in details, and shows the test result of a demo system based on the architecture.

Analysis and Impact of Surface Acoustic Wave Filter in-Band Ripple on Testing and Measurement of High Data Rate Communications

In this paper, we present a background and theory of the effect of Surface Acoustic Wave (SAW) Filter Module (SFM) in-band ripple on high data rate communications parameters such as the Error Vector Magnitude (EVM). In addition, we present analyses and statements for the choice of unbalanced S-parameters set of the SFM over balanced S-parameters set of the SFM in measurements and Agilent’s Advance Design System (ADS) Ptolemy simulations. A test and measurement setup using Agilent’s equipment will be presented.

An Optimal Feed Interpolator Based on G^2 Continuous Bézier Curves for High-Speed Machining of Linear Tool Path

A numerical control (NC) tool path of digital CAD model is widely generated as a set of short line segments in machining. However, there are three shortcomings in the linear tool path, such as discontinuities of tangency and curvature, huge number of line segments, and short lengths of line segments. These disadvantages hinder the development of high speed machining. To smooth the linear tool path and improve machining efficiency of short line segments, this paper presents an optimal feed interpolator based on G^2 continuous Bézier curves for the linear tool path. First, the areas suitable for fitting are screened out based on the geometric characteristics of continuous short segments (CSSs). CSSs in every area are compressed and fitted into a G^2 Continuous Bézier curve by using the least square method. Then a series of cubic Bézier curves are generated. However, the junction between adjacent Bézier curves is only G^0 continuous. By adjusting the control points and inserting Bézier transition curves between adjacent Bézier curves, the G^2 continuous tool path is constructed. The fitting error is estimated by the second-order Taylor formula. Without iteration, the fitting algorithm can be implemented in real-time environment. Second, the optimal feed interpolator considering the comprehensive constraints (such as the chord error constraint, the maximum normal acceleration, servo capacity of each axis, etc.) is proposed. Simulation and experiment are conducted. The results shows that the proposed method can generate smooth path, decrease the amount of segments and reduce machining time for machining of linear tool path. The proposed research provides an effective method for high-speed machining of complex 2-D/3-D profiles described by short line segments.

A fault prediction method for catenary of high-speed rails based on meteorological conditions

Fault frequency of catenary is related to meteo-rological conditions. In this work, based on the historical data, catenary fault frequency and weather-related fault rate are introduced to analyse the correlation between catenary faults and meteorological conditions, and further the effect of meteorological conditions on catenary oper-ation. Moreover, machine learning is used for catenary fault prediction. As with the single decision tree, only a small number of training samples can be classified cor-rectly by each weak classifier, the AdaBoost algorithm is adopted to adjust the weights of misclassified samples and weak classifiers, and train multiple weak classifiers. Finally, the weak classifiers are combined to construct a strong classifier, with which the final prediction result is obtained. In order to validate the prediction method, an example is provided based on the historical data from a railway bureau of China. The result shows that the mapping relation between meteorological conditions and catenary faults can be established accurately by AdaBoost algorithm. The AdaBoost algorithm can accurately predict a catenary fault if the meteorological conditions are provided.

Statistical delay distribution analysis on high-speed railway trains

The focus of this study is to explore the statis-tical distribution models of high-speed railway (HSR) train delays. Based on actual HSR operational data, the delay causes and their classification, delay frequency, number of affected trains, and space–time delay distributions are discussed. Eleven types of delay events are classified, and a detailed analysis of delay distribution for each classifica-tion is presented. Models of delay probability delay prob-ability distribution for each cause are proposed. Different distribution functions, including the lognormal, exponen-tial, gamma, uniform, logistic, and normal distribution, were selected to estimate and model delay patterns. The most appropriate distribution, which can approximate the delay duration corresponding to each cause, is derived. Subsequently, the Kolmogorov–Smirnov (K–S) test was used to test the goodness of fit of different train delay distribution models and the associated parameter values. The test results show that the distribution of the test data is consistent with that of the selected models. The fitting distribution models show the execution effect of the timetable and help in finding out the potential conflicts in real-time train operations.

基于FPGA的多通道高速串行数据采集系统设计

针对卫星导航信号抗干扰领域中进行高精度高速多通道数据采集的需要,系统采用ADI公司的16位高速串行AD转换芯片AD9653,完成模数转换,其转换精度可达16比特,转换速率最高为125MSPS。分析AD9653的高速串行数据接口特点,采用Xilinx公司的Kintex-7系列FPGA提供的片同步技术,进行位时钟自适应相位校准和数据帧调整研究,保证了高速串行数据传输的稳定性与正确性。采用内部FIFO数据缓存的方式实现多通道数据的片内同步以保证后续抗干扰算法的正确处理。研究结果表明,使用该方法进行高速串行数据采集时系统稳定可靠、正确无误。为多通道高速串行数据采集提供了一种切实可行的解决方案,对类似需求的数据采集系统具有一定的参考价值。

数字示波器中FPGA间高速信号传输同步方法

数据采集系统是数字示波器(DSO)的核心组成单元,随着示波器带宽采样率的逐步提升,单片模数转换器(ADC)+现场可编辑门控阵列(FPGA)的架构难以满足超高速以及多通道的应用场景,因此,高端示波器中数据采集系统普遍采用“主从”FPGA控制架构。在该架构下,多个FPGA之间信号的同步传输是实现采集系统的同步和精确采集的重要前提。针对多FPGA板卡之间的信号同步传输问题,提出了一种FPGA之间高速信号同步传输的方法,借助FPGA的IODELAY单元,通过测试数据训练找到最稳定的同步传输区间,实现多FPGA之间的同步传输。在自研的数字示波器上的实验表明,该方法能够有效实现FPGA之间高速信号的同步传输。

高速铁路动检车轴箱加速度与轮轨力数据里程对齐研究

高速铁路动检数据对轨道养护维修具有重要意义,其中轴箱加速度和轮轨力是两种能够反映轨道短波不平顺信息且相互关联的高频采样数据。然而,这两种数据之间存在里程误差,以至于在评价轨道平顺性时无法建立参考基准。现有的动检数据里程修正方法大多需要结合线路台账信息,主要针对轨道几何不平顺数据的里程对齐,鲜有适用于无线路超高信息且高频采样下的轴箱加速度和轮轨力里程对齐方法。提出一种二阶段窗长收敛的里程误差修正模型,结合线性插值方法调整全局波形。根据某高速铁路实测轴箱加速度、轮轨力数据修正结果表明:该线路区间的里程误差在第一阶段修正后从1 km左右减小至42 m以内,经第二阶段精确修正后误差在99.7%的置信度下可控制在1.55 m以内。数据能量趋势结果表明,修正后轴箱加速度、轮轨力数据趋势线性相关性在全区段显著提升。

高速铁路动静态轨检数据里程对齐与误差修正

轨道几何动、静检测数据间的精确匹配对探明高速铁路线路服役状态和制定准确可靠的养护维修策略具有关键作用。针对动静里程匹配算法研究较少的现状,提出利用动、静态实测数据波形匹配,建立基于互相关函数与动态时间规划相结合的两阶段修正算法,并以距离误差作为评价指标。结合某高铁线路轨道几何检测数据的案例分析,以静态检测数据作为参考基准,对动态检测数据进行里程误差评估与修正。结果表明,两阶段算法修正效果显著,累积距离误差降幅超过93%,修正后的动、静态检测数据严格对齐保证了动态检测数据的可靠性与有效性。

基于数据驱动的高速铁路动车组列车头尾车车轮踏面缺陷预测方法

[目的]踏面缺陷是高速铁路动车组列车车轮失效的主要表现形式之一,严重影响了动车组运行的安全性及乘客的乘坐舒适性。车轮踏面缺陷主要集中在头尾车,可能是多种因素共同作用的结果,需要寻找一种能综合多种影响因素的预测方法。[方法]基于某铁路局动车组列车的车轮镟修数据,每个数据样本包括10个特征(4个名义特征和6个连续特征),对数据进行预处理。通过合成少数类样本过采样技术对不平衡数据集进行处理,构建了标准化数据集。建立了DNN(深度神经网络)模型,对底层特征进行组合,形成了特征的高层抽象表示。通过网络结构调整和超参数优化得到了模型的最优学习效果。对模型进行训练并测试,验证了该模型的预测效果。[结果及结论]基于数据驱动的头尾车车轮踏面缺陷预测方法具有较高的预测精度和较优的综合性能,其预测精确率达92.5%,可有效预测头尾车车轮踏面损伤的发生概率。

多GPU系统的高速互联技术与拓扑发展现状研究

多GPU系统通过横向扩展实现性能提升,以满足人工智能日趋复杂的算法和持续激增的数据所带来的不断增长的计算需求。对于多GPU系统而言,处理器间的互联带宽以及系统的拓扑是决定系统性能的关键因素。在传统的基于PCIe的多GPU系统中,PCIe带宽是限制系统性能的瓶颈。当前,面向GPU的高速互联技术成为解决多GPU系统带宽限制问题的有效方法。本文首先介绍了传统多GPU系统所采用的PCIe互联技术及其典型拓扑,然后以Nvidia NVLink、AMD Infinity Fabric Link、Intel X^(e) Link、壁仞科技BLink为例,对国内外代表性GPU厂商的面向GPU的高速互联技术及其拓扑进行了梳理分析,最后讨论了关于互联技术的研究启示。

基于CH579的高速串口服务器

针对目前的串口到网口数据透传模块存在传输速度慢、稳定性差、串口参数无法远程配置等问题,设计了一种基于CH579型号单片机的高速串口转以太网服务器。该系统通过采用串口八级FIFO缓存方式提高数据传输速率,通过优化串口成帧机制降低丢包率从而提高系统稳定性,通过设计串口参数配置协议实现上位机对串口参数的远程配置。测试结果表明:系统进行透明传输时串口最高波特率能达到5 Mbit/s,平均丢包率为0.0650%。因此该系统在提高串口波特率,提升系统稳定性和通用性上有明显改善。

基于NVMe-oF的高速大容量存储系统设计

随着信息技术的快速发展,数据规模和数据类型持续增长,为了高效存储数据、充分挖掘数据价值,需要快速提升存储系统的存储容量,增强读写性能,因此,对高速大容量存储技术进行深入研究的需求愈发迫切。文章基于NVMe-oF技术设计了一个高速大容量存储系统。该系统能够提供端到端的高带宽、低延迟数据存储,相较传统存储系统实现了计算与存储资源的解耦,能够支撑后期根据需求对计算、存储资源的适应性灵活升级扩容。

基于FPGA的OFDM接收机处理数据高速传输系统

根据正交频分复用(OFDM)接收机处理数据的高速传输需求,设计一种基于FPGA万兆以太网的高速传输系统。系统对子带、窄带和频谱子信道数据进行处理和储存,按照规定的自定义协议将数据组包,采用UDP/IP协议栈对数据包网络数据打包,通过万兆光口传输至服务器。测试结果表明,该方案能够通过指定的协议高速实时地将多种信道化数据传输至服务器,实时传输速率高达5.7千兆字节/秒。该系统稳定性高、数据实时性高、控制时序精确,适合作为OFDM接收机处理数据的传输系统。

基于HXDSP JESD204B的高速数据采集系统设计

在航天航空、工业仪器仪表、矿物勘探等各个领域,对关键数据的高速采集和后续的处理都相当重要,JESD204B协议是目前通用的高速ADC/DAC标准串行通信协议。本文设计了一种基于JESD204B协议的高速数据采集系统,系统基于国产DSP芯片HX1041和GAD14D1GEE型AD转换器构建了一个高速数据采集平台,实验表明该平台可以实现数据的采集与实时处理。

传输网络中基于光纤的高速数据传输技术探索

文章深入研究了基于光纤的高速数据传输技术,介绍了光纤传输的基本原理,通过光的全反射实现光信号的快速传输。系统组成与架构方面,讨论了发光器、光纤电缆、光纤放大器以及光解调器等关键组件。接着,分析了传输网络中高速数据传输的需求和光纤传输中的挑战。在技术探索方面,深入研究了信号调制与解调技术、光纤放大器与信号增强技术,以及针对挑战的高速数据传输优化策略。通过对这些关键领域的分析,旨在为高速数据传输提供全面的技术支持,促进信息时代的高效、可靠数据传输。