Force and impulse multi-sensor based on flexible gate dielectric field effect transistor

Nowadays,force sensors play an important role in industrial production,electronic information,medical health,and many other fields.Two-dimensional material-based filed effect transistor(2D-FET)sensors are competitive with nano-level size,lower power consumption,and accurate response.However,few of them has the capability of impulse detection which is a path function,expressing the cumulative effect of the force on the particle over a period of time.Herein we fabricated the flexible polymethyl methacrylate(PMMA)gate dielectric MoS_(2)-FET for force and impulse sensor application.We systematically investigated the responses of the sensor to constant force and varying forces,and achieved the conversion factors of the drain current signals(I_(ds))to the detected impulse(I).The applied force was detected and recorded by I_(ds)with a low power consumption of~30 nW.The sensitivity of the device can reach~8000%and the 4×1 sensor array is able to detect and locate the normal force applied on it.Moreover,there was almost no performance loss for the device as left in the air for two months.

Effect of High-Gate-Voltage Stress on the Reverse Gated-Diode Current in LDD nMOSFET’s

The reverse generation current under high-gate-voltage stress condition in LDD nMOSFET＇s is studied. We find that the generation current peak decreases as the stress time increases. We ascribe this finding to the dominating oxide trapped electrons that reduce the effective drain bias, lowering the maximal generation rate. The density of the effective trapped electrons affecting the effective drain bias is calculated with our model.

引入上下文信息和Attention Gate的GUS-YOLO遥感目标检测算法

目前基于通用YOLO系列的遥感目标检测算法存在并未充分利用图像的全局上下文信息,在特征融合金字塔部分并未充分考虑缩小融合特征之间的语义鸿沟、抑制冗余信息干扰的缺点。在结合YOLO算法优点的基础上提出GUS-YOLO算法,其拥有一个能够充分利用全局上下文信息的骨干网络Global Backbone。除此之外,该算法在融合特征金字塔自顶向下的结构中引入Attention Gate模块,可以突出必要的特征信息,抑制冗余信息。另外,为Attention Gate模块设计了最佳的网络结构,提出了网络的特征融合结构U-Net。最后,为克服ReLU函数可能导致模型梯度不再更新的问题,该算法将Attention Gate模块的激活函数升级为可学习的SMU激活函数,提高模型鲁棒性。在NWPU VHR-10遥感数据集上,该算法相较于YOLOV7算法取得宽松指标mAP^(0.50)1.64个百分点和严格指标mAP^(0.75)9.39个百分点的性能提升。相较于目前主流的七种检测算法,该算法取得较好的检测性能。

Modeling of Gate Tunneling Current for Nanoscale MOSFETs with High-k Gate Stacks

A quantum model based on solutions to the Schrodinger-Poisson equations is developed to investigate the device behavior related togate tunneling current for nanoscale MOSFETs with high-k gate stacks. This model can model various MOS device structures with combinations of high-k dielectric materials and multilayer gate stacks,revealing quantum effects on the device performance. Comparisons are made for gate current behavior between nMOSFET and pMOSFET high- k gate stack structures. The results presented are consistent with experimental data, whereas a new finding for an optimum nitrogen content in HfSiON gate dielectric requires further experimental verifications.

Characteristics of high-quality HfSiON gate dielectric prepared by physical vapour deposition

This paper presents a method using simple physical vapour deposition to form high-quality hafnium silicon oxynitride （HfSiON） on ultrathin SiO2 buffer layer. The gate dielectric with 10A （1A = 0.1 nm） equivalent oxide thickness is obtained. The experimental results indicate that the prepared HfSiON gate dielectric exhibits good physical and electrical characteristics, including very good thermal stability up to 1000℃, excellent interface properties, high dielectric constant （k = 14） and low gate-leakage current （Ig = 1.9 × 10^-3 A/cm^2@Vg = Vfb - 1 V for EOT of 10 A）. TaN metal gate electrode is integrated with the HfSiON gate dielectric.The effective work function of TaN on HfSiON is 4.3 eV, meeting the requirements of NMOS for the metal gate. And, the impacts of sputtering ambient and annealing temperature on the electrical properties of HfSiON gate dielectric are investigated.

Phase control of magnetron sputtering deposited Gd_2O_3 thin films as high-κ gate dielectrics

Gd2O3 thin films as high-κ gate dielectrics were deposited directly on Si（001） substrates by magnetron sputtering at a pressure of 1.3 Pa and different temperatures. X-ray diffraction results revealed that all the films grown from 450 to 570 ℃ were crystalline, and the Gd2O3 thin films consisted of a mixture of cubic and monoclinic phases. The growth temperature was a critical parameter for the phase constituents and their relative amount. Low temperature was favorable for the formation of cubic phase while higher temperature gave rise to more monoclinic phase. All the Gd2O3 thin films grown from different temperatures exhibited acceptable electrical properties, such as low leakage current density （JL） of 10-5 A/cm^2 at zero bias with capacitance equivalent SiO2 thickness in the range of 6-13 nm. Through the comparison between films grown at 450 and 570 ℃, the existence of monoclinic phase caused an increase in JL by nearly one order of magnitude and a reduction of effective dielectric constant from 17 to 9.

Challenges in Atomic-Scale Characterization of High-k Dielectrics and Metal Gate Electrodes for Advanced CMOS Gate Stacks

The decreasing feature sizes in complementary metal-oxide semiconductor （CMOS） transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant （high-k） because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability. In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology. Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties. It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling. In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices. Therefore, detailed atomic- scale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks, are highly required. In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed. Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy （HRTEM） and the related techniques based on scanning transmission electron microscopy （STEM）, including high-angle annular dark- field （HAADF） imaging （also known as Z-contrast imaging）, electron energy-loss spectroscopy （EELS）, and energy dispersive X-ray spectroscopy （EDS）, due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric gate stacks in the present and future generations of CMOS devices. In Section 1 of this review, the working principles of each technique are briefly introduced and their key features are outlined. In Section 2, microstructural characterizations of high-k gate dielectrics at atomic-scale by electron microscopy are critically reviewed by citing some recent results reported on high-k gate dielectrics. In Section 3, metal gate electrodes and the interfacial structures between high-k dielectrics and metal gates are discussed. The electron beam damage effects in high-k gate stacks are also evaluated, and their origins and prevention are described in Section 4. Finally, we end this review with personal perspectives towards the future challenges of atomic-scale material characterization in advanced CMOS gate stacks.

High performance trench MOS barrier Schottky diode with high-k gate oxide

A novel trench MOS barrier Schottky diode（TMBS） device with a high-k material introduced into the gate insulator is reported, which is named high-k TMBS. By simulation with Medici, it is found that the high-k TMBS can have 19.8% lower leakage current while maintaining the same breakdown voltage and forward turn-on voltage compared with the conventional regular trench TMBS.

High-k gate dielectric GaAs MOS device with LaON as interlayer and NH_3-plasma surface pretreatment

High-k gate dielectric Hf Ti ON Ga As metal-oxide–semiconductor（MOS） capacitors with La ON as interfacial passivation layer（IPL） and NH3- or N2-plasma surface pretreatment are fabricated, and their interfacial and electrical properties are investigated and compared with their counterparts that have neither La ON IPL nor surface treatment. It is found that good interface quality and excellent electrical properties can be achieved for a NH3-plasma pretreated Ga As MOS device with a stacked gate dielectric of Hf Ti ON/La ON. These improvements should be ascribed to the fact that the NH3-plasma can provide H atoms and NH radicals that can effectively remove defective Ga/As oxides. In addition, La ON IPL can further block oxygen atoms from being in-diffused, and Ga and As atoms from being out-diffused from the substrate to the high-k dielectric. This greatly suppresses the formation of Ga/As native oxides and gives rise to an excellent high-k/Ga As interface.

Electronic mobility in the high-carrier-density limit of ion gel gated IDTBT thin film transistors

Indacenodithiophene-co-benzothiadiazole（IDTBT） has emerged as one of the most exciting semiconducting polymers in recent years because of its high electronic mobility and charge transport along the polymer backbone. By using the recently developed ion gel gating technique we studied the charge transport of IDTBT at carrier densities up to 10^21cm^-3.While the conductivity in IDTBT was found to be enhanced by nearly six orders of magnitude by ionic gating, the charge transport in IDTBT was found to remain 3D Mott variable range hopping even down to the lowest temperature of our measurements, 12 K. The maximum mobility was found to be around 0.2 cm^2·V^-1·s^-1, lower than that of Cytop gated field effect transistors reported previously. We attribute the lower mobility to the additional disorder induced by the ionic gating.

Current Progress of Hf(Zr)-Based High-k Gate Dielectric Thin Films

With the continued downscaling of complementary metal-oxide-semiconductor field effect transistor dimensions, high-dielectric constant （high-k） gate materials, as alternatives to SiO2, have been extensively investigated. Hf （Zr）-based high-k gate dielectric thin films have been regarded as the most promising candidates for high-k gate dielectric according to the International Technology Roadmap for Semiconductor due to their excellent physical properties and performance. This paper reviews the recent progress on Hf （Zr）-based high-k gate dielectrics based on PVD （physical vapor deposition） process. This article begins with a survey of various methods developed for generating Hf （Zr）-based high-k gate dielectrics, and then mainly focuses on microstructure, synthesis, characterization, formation mechanisms of interfacial layer, and optical properties of Hf （Zr）-based high-k gate dielectrics. Finally, this review concludes with personal perspectives towards future research on Hf （Zr）-based high-k gate dielectrics.

All-optical logic gate computing for high-speed parallel information processing

Optical computing and optical neural network have gained increasing attention in recent years because of their potential advantages of parallel processing at the speed of light and low power consumption by comparison with electronic computing.The optical implementation of the fundamental building blocks of a digital computer,i.e.logic gates,has been investigated extensively in the past few decades.Optical logic gate computing is an alternative approach to various analogue optical computing architectures.In this paper,the latest development of optical logic gate computing with different kinds of implementations is reviewed.Firstly,the basic concepts of analogue and digital computing with logic gates in the electronic and optical domains are introduced.And then a comprehensive summary of various optical logic gate schemes including spatial encoding of light field,semiconductor optical amplifiers(SOA),highly nonlinear fiber(HNLF),microscale and nanoscale waveguides,and photonic crystal structures is presented.To conclude,the formidable challenges in developing practical all-optical logic gates are analyzed and the prospects of the future are discussed.

The influence and explanation of fringing-induced barrier lowering on sub-100 nm MOSFETs with high-k gate dielectrics

The fringing-induced barrier lowering（FIBL） effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator.An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect.The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance.Based on equivalent capacitance theory,the influences of channel length,junction depth,gate/lightly doped drain（LDD） overlap length,spacer material and spacer width on FIBL is thoroughly investigated.A stack gate dielectric is presented to suppress the FIBL effect.

Analysis of flatband voltage shift of metal/high-k/SiO_2/Si stack based on energy band alignment of entire gate stack

A theoretical model of flatband voltage （VFB） of metal/high-k/Si02/Si stack is proposed based on band alignment of entire gate stack, i.e., the VFB is obtained by simultaneously considering band alignments of metal/high-k, high-k/SiO2 and SiO2/Si interfaces, and their interactions. Then the VFB of TiN/HfO2/SiO2/Si stack is experimentally obtained and theoretically investigated by this model. The theoretical calculations are in good agreement with the experimental results. Furthermore, both positive VFB shift of TiN/HfO2/SiO2/Si stack and Fermi level pinning are successfully interpreted and attributed to the dielectric contact induced gap states at TiN/HfO2 and HfO2/SiO2 interfaces.

Key technologies for dual high-k and dual metal gate integration

The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the wafer, and the synchronous etching of n/pMOS gate stack, are successfully developed. First, reasonable flat-band voltage and equivalent oxide thickness of pMOS MIPS structure are obtained by further optimizing the HfSiAlON dielectric through incorporating more Al-O dipole at interface between HfSiAlON and bottom SiOx. Then, the separating of high-k and metal gate for n/pMOS is achieved by SC1（NH4OH：H2O2：H2O = 1 ： 1 ： 5） and DHF-based solution for the selective removing of n MOS TaN and Hf Si ON and by BCl3-based plasma and DHF-based solution for the selective removing of pMOS TaN/Mo and HfSiAlON.After that, the synchronous etching of n/pMOS gate stack is developed by utilizing optimized BCl3/SF6/O2/Ar plasma to obtain a vertical profile for TaN and TaN/Mo and by utilizing BCl3/Ar plasma combined with DHF-based solution to achieve high selectivity to Si substrate. Finally, good electrical characteristics of CMOS devices, obtained by utilizing these new developed technologies, further confirm that they are practicable technologies for DHDMG integration.

Flat-band voltage shift in metal-gate/high-k/Si stacks

In metal-gate/high-k stacks adopted by the 45 nm technology node, the fiat-band voltage （Vfb） shift remains one of the most critical challenges, particularly the flat-band voltage roll-off （Vfb roll-off） phenomenon in p-channel metal- oxide-semiconductor （pMOS） devices with an ultrathin oxide layer. In this paper, recent progress on the investigation of the Vfb shift and the origin of the Vfb roll-off in the metal-gate/high-k pMOS stacks are reviewed. Methods that can alleviate the Vfb shift phenomenon are summarized and the future research trend is described.

Heralded entanglement purification protocol using high-fidelity parity-check gate based on nitrogen-vacancy center in optical cavity

The decoherence of entangled states caused by the noisy channel is a salient problem for reducing the fidelity of quantum communication.Here we present a heralded two-photon entanglement purification protocol(EPP)using heralded high-fidelity parity-check gate(HH-PCG),which can increase the entanglement of nonlocal two-photon polarization mixed state.The HH-PCG is constructed by the input-output process of nitrogen-vacancy(NV)center in diamond embedded in a single-sided optical cavity,where the errors caused by the imperfect interaction between the NV center-cavity system and the photon can be heralded by the photon detector.As the unwanted components can be filtrated due to the heralded function,the fidelity of the EPP scheme can be enhanced considerably,which will increase the fidelity of quantum communication processing.

Study on influences of TiN capping layer on time-dependent dielectric breakdown characteristic of ultra-thin EOT high-k metal gate NMOSFET with kMC TDDB simulations

The thickness effect of the TiN capping layer on the time dependent dielectric breakdown（TDDB） characteristic of ultra-thin EOT high-k metal gate NMOSFET is investigated in this paper.Based on experimental results,it is found that the device with a thicker TiN layer has a more promising reliability characteristic than that with a thinner TiN layer.From the charge pumping measurement and secondary ion mass spectroscopy（SIMS） analysis,it is indicated that the sample with the thicker TiN layer introduces more Cl passivation at the IL/Si interface and exhibits a lower interface trap density.In addition,the influences of interface and bulk trap density ratio Nit/Not are studied by TDDB simulations through combining percolation theory and the kinetic Monte Carlo（kMC） method.The lifetime reduction and Weibull slope lowering are explained by interface trap effects for TiN capping layers with different thicknesses.

Temperature- and voltage-dependent trap generation model in high-k metal gate MOS device with percolation simulation

High-k metal gate stacks are being used to suppress the gate leakage due to tunneling for sub-45 nm technology nodes.The reliability of thin dielectric films becomes a limitation to device manufacturing,especially to the breakdown characteristic.In this work,a breakdown simulator based on a percolation model and the kinetic Monte Carlo method is set up,and the intrinsic relation between time to breakdown and trap generation rate R is studied by TDDB simulation.It is found that all degradation factors,such as trap generation rate time exponent m,Weibull slope β and percolation factor s,each could be expressed as a function of trap density time exponent α.Based on the percolation relation and power law lifetime projection,a temperature related trap generation model is proposed.The validity of this model is confirmed by comparing with experiment results.For other device and material conditions,the percolation relation provides a new way to study the relationship between trap generation and lifetime projection.

Analytical model including the fringing-induced barrier lowering effect for a dual-material surrounding-gate MOSFET with a high-κ gate dielectric

By solving Poisson＇s equation in both semiconductor and gate insulator regions in the cylindrical coordinates, an analytical model for a dual-material surrounding-gate （DMSG） metal-oxide semiconductor field-effect transistor （MOSFET） with a high-k gate dielectric has been developed. Using the derived model, the influences of fringing-induced barrier lowering （FIBL） on surface potential, subthreshold current, DIBL, and subthreshold swing are investigated. It is found that for the same equivalent oxide thickness, the gate insulator with high-k dielectric degrades the short-channel performance of the DMSG MOSFET. The accuracy of the analytical model is verified by the good agreement of its results with that obtained from the ISE three-dimensional numerical device simulator.