There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon...There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.展开更多
目标检测器现已被广泛应用在各类智能系统中,主要用于对图像中的物体进行识别与定位.然而,近年来的研究表明,目标检测器与DNNs分类器都易受数字对抗样本和物理对抗样本的影响.YOLOv3是实时检测任务中一种主流的目标检测器,现有攻击YOLOv...目标检测器现已被广泛应用在各类智能系统中,主要用于对图像中的物体进行识别与定位.然而,近年来的研究表明,目标检测器与DNNs分类器都易受数字对抗样本和物理对抗样本的影响.YOLOv3是实时检测任务中一种主流的目标检测器,现有攻击YOLOv3的物理对抗样本的构造方式大多是将生成的较大对抗性扰动打印出来再粘贴在特定类别的物体表面.最近的研究中出现的假阳性对抗样本(false positive adversarial example,FPAE)可通过目标模型直接生成得到,人无法识别出该对抗样本图像中的内容,但目标检测器却以高置信度将其误识别为攻击者指定的目标类.现有以YOLOv3为目标模型生成FPAE的方法仅有AA(appearing attack)方法一种,该方法在生成FPAE的过程中,为提升FPAE的鲁棒性,会在迭代优化过程中加入EOT(expectation over transformation)图像变换来模拟各种物理条件,但是并未考虑拍摄时可能出现的运动模糊(motion blur)情况,进而影响到对抗样本的攻击效果.此外,生成的FPAE在对除YOLOv3外的目标检测器进行黑盒攻击时的攻击成功率并不高.为生成性能更好的FPAE,以揭示现有目标检测器存在的弱点和测试现有目标检测器的安全性,以YOLOv3目标检测器为目标模型,提出RTFP(robust and transferable false positive)对抗攻击方法.该方法在迭代优化过程中,除了加入典型的图像变换外,还新加入了运动模糊变换.同时,在损失函数的设计上,借鉴了C&W攻击中损失函数的设计思想,并将目标模型在FPAE的中心所在的网格预测出的边界框与FPAE所在的真实边界框之间的重合度(intersection over union,IOU)作为预测的边界框的类别损失的权重项.在现实世界中的多角度、多距离拍摄测试以及实际道路上的驾车拍摄测试中,RTFP方法生成的FPAE能够保持较强的鲁棒性且迁移性强于现有方法生成的FPAE.展开更多
基金supported in part by the National Natural Science Foundation of China(Nos.12005245,12075100,and 11775244)by the Scientific and Technological Innovation Project(No.2020000165)from the Institute of High Energy Physics,Chinese Academy of Sciences+1 种基金partially funded by the Scientific Instrument Development Project of the Chinese Academy of Sciences(No.ZDKYYQ20200007)Youth Innovation Promotion Association of the Chinese Academy of Sciences(No.Y201905).
文摘There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.
文摘目标检测器现已被广泛应用在各类智能系统中,主要用于对图像中的物体进行识别与定位.然而,近年来的研究表明,目标检测器与DNNs分类器都易受数字对抗样本和物理对抗样本的影响.YOLOv3是实时检测任务中一种主流的目标检测器,现有攻击YOLOv3的物理对抗样本的构造方式大多是将生成的较大对抗性扰动打印出来再粘贴在特定类别的物体表面.最近的研究中出现的假阳性对抗样本(false positive adversarial example,FPAE)可通过目标模型直接生成得到,人无法识别出该对抗样本图像中的内容,但目标检测器却以高置信度将其误识别为攻击者指定的目标类.现有以YOLOv3为目标模型生成FPAE的方法仅有AA(appearing attack)方法一种,该方法在生成FPAE的过程中,为提升FPAE的鲁棒性,会在迭代优化过程中加入EOT(expectation over transformation)图像变换来模拟各种物理条件,但是并未考虑拍摄时可能出现的运动模糊(motion blur)情况,进而影响到对抗样本的攻击效果.此外,生成的FPAE在对除YOLOv3外的目标检测器进行黑盒攻击时的攻击成功率并不高.为生成性能更好的FPAE,以揭示现有目标检测器存在的弱点和测试现有目标检测器的安全性,以YOLOv3目标检测器为目标模型,提出RTFP(robust and transferable false positive)对抗攻击方法.该方法在迭代优化过程中,除了加入典型的图像变换外,还新加入了运动模糊变换.同时,在损失函数的设计上,借鉴了C&W攻击中损失函数的设计思想,并将目标模型在FPAE的中心所在的网格预测出的边界框与FPAE所在的真实边界框之间的重合度(intersection over union,IOU)作为预测的边界框的类别损失的权重项.在现实世界中的多角度、多距离拍摄测试以及实际道路上的驾车拍摄测试中,RTFP方法生成的FPAE能够保持较强的鲁棒性且迁移性强于现有方法生成的FPAE.
