The demands of programmability have become more and more exigent as novel network services appear, such as E-commerce, social softwares, and online videos. Commodity multi-core CPUs have been widely applied in network...The demands of programmability have become more and more exigent as novel network services appear, such as E-commerce, social softwares, and online videos. Commodity multi-core CPUs have been widely applied in network packet processing to get high programmability and reduce the time-to-market. However,there is a great gap between the packet processing performance of commodity multi-core and that of the traditional packet processing hardware, e.g., NP(Network Process). Recently, optimization of the packet processing performance of commodity multi-cores has become a hot topic in industry and academia. In this paper, based on a detailed analysis of the packet processing procedure, firstly we identify two dominating overheads, namely the virtual-to-physical address translation and the packet buffer management. Secondly, we make a comprehensive survey on the current optimization methods. Thirdly, based on the survey, the heterogeneous architecture of the commodity multi-core + FPGA is proposed as a promising way to improve the packet processing performance.Fourthly, a novel Self-Described Buffer(SDB) management technology is introduced to eliminate the overheads of the allocation and deallocation of the packet buffers offloaded to FPGA. Then, an evaluation testbed, named PIOT(Packet I/O Testbed), is designed and implemented to evaluate the packet forwarding performance. I/O capacity of different commodity multi-core CPUs and the performance of optimization methods are assessed and compared based on PIOT. At last, the future work of packet processing optimization on multi-core CPUs is discussed.展开更多
The packet size of bainitic steel can be refined by a specialrelaxation-precipitation-control phase transformation (RFC) technology. When processed by RPCprocess, the low carbon bainitic steel composes of two kinds of...The packet size of bainitic steel can be refined by a specialrelaxation-precipitation-control phase transformation (RFC) technology. When processed by RPCprocess, the low carbon bainitic steel composes of two kinds of main intermediate transformationphases. One is ultra-fine lath-like bainitic ferrite and the lath is less than 1μm in width andabout 6 μm in length; the alignment of laths forms a refined packet, and the size of packets isabout 5-7 μm in length and about 3-4μm in width. The other is acicular structure. The morphologyand distribution of these acicular structures are influenced by relaxation process, the thin andshort acicular structures cut the prior austenite grain and refine the bainitic packet size. For theoptimum relaxation time, the packet size can be refined to the finest. The mechanical propertiesare influenced by relaxation time and the 800 MPa grade low carbon bainitic steel with excellenttoughness can be obtained by RPC process.展开更多
The packet classification is a fundamental process in provisioning security and quality of service for many intelligent network-embedded systems running in the Internet of Things(IoT).In recent years,researchers have ...The packet classification is a fundamental process in provisioning security and quality of service for many intelligent network-embedded systems running in the Internet of Things(IoT).In recent years,researchers have tried to develop hardware-based solutions for the classification of Internet packets.Due to higher throughput and shorter delays,these solutions are considered as a major key to improving the quality of services.Most of these efforts have attempted to implement a software algorithm on the FPGA to reduce the processing time and enhance the throughput.The proposed architectures,however,cannot reach a compromise among power consumption,memory usage,and throughput rate.In view of this,the architecture proposed in this paper contains a pipelinebased micro-core that is used in network processors to classify packets.To this end,three architectures have been implemented using the proposed micro-core.The first architecture performs parallel classification based on header fields.The second one classifies packets in a serial manner.The last architecture is the pipeline-based classifier,which can increase performance by nine times.The proposed architectures have been implemented on an FPGA chip.The results are indicative of a reduction in memory usage as well as an increase in speedup and throughput.The architecture has a power consumption of is 1.294w,and its throughput with a frequency of 233 MHz exceeds 147 Gbps.展开更多
This paper presents a novel method for radar emitter signal recognition. First, wavelet packet transform （WPT） is introduced to extract features from radar emitter signals. Then, rough set theory is used to select t...This paper presents a novel method for radar emitter signal recognition. First, wavelet packet transform （WPT） is introduced to extract features from radar emitter signals. Then, rough set theory is used to select the optimal feature subset with good discriminability from original feature set, and support vector machines （SVMs） are employed to design classifiers. A large number of experimental results show that the proposed method achieves very high recognition rates for 9 radar emitter signals in a wide range of signal-to-noise rates, and proves a feasible and valid method.展开更多
Design and implementation of Internet of Things (IoT) systems require platforms with smart things and components. Two dominant architectural approaches for developing IoT systems are mashup-based and model-based appro...Design and implementation of Internet of Things (IoT) systems require platforms with smart things and components. Two dominant architectural approaches for developing IoT systems are mashup-based and model-based approaches. Mashup approaches use existing services and are mainly suitable for less critical, personalized applications. Web development tools are widely used in mashup approaches. Model-based techniques describe a system on a higher level of abstraction, resulting in very expressive modelling of systems. The article uses Cisco packet tracer 7.2 version, which consists of four subcategories of smart things—home, smart city, industrial and power grid, to design an IoT based control system for a fertilizer manufacturing plant. The packet tracer also consists of boards—microcontrollers (MCU-PT), and single boarded computers (SBC-PT), as well as actuators and sensors. The model facilitates flexible communication opportunities among things—machines, databases, and Human Machine Interfaces (HMIs). Implementation of the IoT system brings finer process control as the operating conditions are monitored online and are broadcasted to all stakeholders in real-time for quicker action on deviations. The model developed focuses on three process plants;steam raising, nitric acid, and ammonium nitrate plants. Key process parameters are saturated steam temperature, fuel flowrates, CO and SO<sub>x</sub> emissions, converter head temperature, NO<sub>x</sub> emissions, neutralisation temperature, solution temperature, and evaporator steam pressure. The parameters need to be monitored in order to ensure quality, safety, and efficiency. Through the Cisco packet tracer platform, a use case, physical layout, network layout, IoT layout, configuration, and simulation interface were developed.展开更多
An analysis of the received signal of array antennas shows that the received signal has multi-resolution characteristics, and hence the wavelet packet theory can be used to detect the signal. By emplying wavelet packe...An analysis of the received signal of array antennas shows that the received signal has multi-resolution characteristics, and hence the wavelet packet theory can be used to detect the signal. By emplying wavelet packet theory to adaptive beamforming, a wavelet packet transform-based adaptive beamforming algorithm (WP-ABF) is proposed . This WP-ABF algorithm uses wavelet packet transform as the preprocessing, and the wavelet packet transformed signal uses least mean square algorithm to implement the ~adaptive beamforming. White noise can be wiped off under wavelet packet transform according to the different characteristics of signal and white under the wavelet packet transform. Theoretical analysis and simulations demonstrate that the proposed WP-ABF algorithm converges faster than the conventional adaptive beamforming algorithm and the wavelet transform-based beamforming algorithm. Simulation results also reveal that the convergence of the algorithm relates closely to the wavelet base and series; that is, the algorithm convergence gets better with the increasing of series, and for the same series of wavelet base the convergence gets better with the increasing of regularity.展开更多
基金supported by National High-tech R&D Program of China(863 Program)(Grant No.2015AA0156-03)National Natural Science Foundation of China(Grant No.61202483)
文摘The demands of programmability have become more and more exigent as novel network services appear, such as E-commerce, social softwares, and online videos. Commodity multi-core CPUs have been widely applied in network packet processing to get high programmability and reduce the time-to-market. However,there is a great gap between the packet processing performance of commodity multi-core and that of the traditional packet processing hardware, e.g., NP(Network Process). Recently, optimization of the packet processing performance of commodity multi-cores has become a hot topic in industry and academia. In this paper, based on a detailed analysis of the packet processing procedure, firstly we identify two dominating overheads, namely the virtual-to-physical address translation and the packet buffer management. Secondly, we make a comprehensive survey on the current optimization methods. Thirdly, based on the survey, the heterogeneous architecture of the commodity multi-core + FPGA is proposed as a promising way to improve the packet processing performance.Fourthly, a novel Self-Described Buffer(SDB) management technology is introduced to eliminate the overheads of the allocation and deallocation of the packet buffers offloaded to FPGA. Then, an evaluation testbed, named PIOT(Packet I/O Testbed), is designed and implemented to evaluate the packet forwarding performance. I/O capacity of different commodity multi-core CPUs and the performance of optimization methods are assessed and compared based on PIOT. At last, the future work of packet processing optimization on multi-core CPUs is discussed.
基金This work was financially supported by National Key Basic Research and Development Program of China (No.G1998061507) and Niobium Steel Development Project of CITIC-CBMM (No.2002RMJS-KY001)
文摘The packet size of bainitic steel can be refined by a specialrelaxation-precipitation-control phase transformation (RFC) technology. When processed by RPCprocess, the low carbon bainitic steel composes of two kinds of main intermediate transformationphases. One is ultra-fine lath-like bainitic ferrite and the lath is less than 1μm in width andabout 6 μm in length; the alignment of laths forms a refined packet, and the size of packets isabout 5-7 μm in length and about 3-4μm in width. The other is acicular structure. The morphologyand distribution of these acicular structures are influenced by relaxation process, the thin andshort acicular structures cut the prior austenite grain and refine the bainitic packet size. For theoptimum relaxation time, the packet size can be refined to the finest. The mechanical propertiesare influenced by relaxation time and the 800 MPa grade low carbon bainitic steel with excellenttoughness can be obtained by RPC process.
文摘The packet classification is a fundamental process in provisioning security and quality of service for many intelligent network-embedded systems running in the Internet of Things(IoT).In recent years,researchers have tried to develop hardware-based solutions for the classification of Internet packets.Due to higher throughput and shorter delays,these solutions are considered as a major key to improving the quality of services.Most of these efforts have attempted to implement a software algorithm on the FPGA to reduce the processing time and enhance the throughput.The proposed architectures,however,cannot reach a compromise among power consumption,memory usage,and throughput rate.In view of this,the architecture proposed in this paper contains a pipelinebased micro-core that is used in network processors to classify packets.To this end,three architectures have been implemented using the proposed micro-core.The first architecture performs parallel classification based on header fields.The second one classifies packets in a serial manner.The last architecture is the pipeline-based classifier,which can increase performance by nine times.The proposed architectures have been implemented on an FPGA chip.The results are indicative of a reduction in memory usage as well as an increase in speedup and throughput.The architecture has a power consumption of is 1.294w,and its throughput with a frequency of 233 MHz exceeds 147 Gbps.
文摘This paper presents a novel method for radar emitter signal recognition. First, wavelet packet transform （WPT） is introduced to extract features from radar emitter signals. Then, rough set theory is used to select the optimal feature subset with good discriminability from original feature set, and support vector machines （SVMs） are employed to design classifiers. A large number of experimental results show that the proposed method achieves very high recognition rates for 9 radar emitter signals in a wide range of signal-to-noise rates, and proves a feasible and valid method.
文摘Design and implementation of Internet of Things (IoT) systems require platforms with smart things and components. Two dominant architectural approaches for developing IoT systems are mashup-based and model-based approaches. Mashup approaches use existing services and are mainly suitable for less critical, personalized applications. Web development tools are widely used in mashup approaches. Model-based techniques describe a system on a higher level of abstraction, resulting in very expressive modelling of systems. The article uses Cisco packet tracer 7.2 version, which consists of four subcategories of smart things—home, smart city, industrial and power grid, to design an IoT based control system for a fertilizer manufacturing plant. The packet tracer also consists of boards—microcontrollers (MCU-PT), and single boarded computers (SBC-PT), as well as actuators and sensors. The model facilitates flexible communication opportunities among things—machines, databases, and Human Machine Interfaces (HMIs). Implementation of the IoT system brings finer process control as the operating conditions are monitored online and are broadcasted to all stakeholders in real-time for quicker action on deviations. The model developed focuses on three process plants;steam raising, nitric acid, and ammonium nitrate plants. Key process parameters are saturated steam temperature, fuel flowrates, CO and SO<sub>x</sub> emissions, converter head temperature, NO<sub>x</sub> emissions, neutralisation temperature, solution temperature, and evaporator steam pressure. The parameters need to be monitored in order to ensure quality, safety, and efficiency. Through the Cisco packet tracer platform, a use case, physical layout, network layout, IoT layout, configuration, and simulation interface were developed.
文摘An analysis of the received signal of array antennas shows that the received signal has multi-resolution characteristics, and hence the wavelet packet theory can be used to detect the signal. By emplying wavelet packet theory to adaptive beamforming, a wavelet packet transform-based adaptive beamforming algorithm (WP-ABF) is proposed . This WP-ABF algorithm uses wavelet packet transform as the preprocessing, and the wavelet packet transformed signal uses least mean square algorithm to implement the ~adaptive beamforming. White noise can be wiped off under wavelet packet transform according to the different characteristics of signal and white under the wavelet packet transform. Theoretical analysis and simulations demonstrate that the proposed WP-ABF algorithm converges faster than the conventional adaptive beamforming algorithm and the wavelet transform-based beamforming algorithm. Simulation results also reveal that the convergence of the algorithm relates closely to the wavelet base and series; that is, the algorithm convergence gets better with the increasing of series, and for the same series of wavelet base the convergence gets better with the increasing of regularity.
