An in-situ self-etching enabled high-power electrode for aqueous zinc-ion batteries

Sluggish storage kinetics is considered as the main bottleneck of cathode materials for fast-charging aqueous zinc-ion batteries(AZIBs).In this report,we propose a novel in-situ self-etching strategy to unlock the Palm tree-like vanadium oxide/carbon nanofiber membrane(P-VO/C)as a robust freestanding electrode.Comprehensive investigations including the finite element simulation,in-situ X-ray diffraction,and in-situ electrochemical impedance spectroscopy disclosed it an electrochemically induced phase transformation mechanism from VO to layered Zn_(x)V_(2)O_5·nH_(2)O,as well as superior storage kinetics with ultrahigh pseudocapacitive contribution.As demonstrated,such electrode can remain a specific capacity of 285 mA h g^(-1)after 100 cycles at 1 A g^(-1),144.4 mA h g^(-1)after 1500 cycles at 30 A g^(-1),and even 97 mA h g^(-1)after 3000 cycles at 60 A g^(-1),respectively.Unexpectedly,an impressive power density of 78.9 kW kg^(-1)at the super-high current density of 100 A g^(-1)also can be achieved.Such design concept of in-situ self-etching free-standing electrode can provide a brand-new insight into extending the pseudocapacitive storage limit,so as to promote the development of high-power energy storage devices including but not limited to AZIBs.

An open-end high-power microwave-induced fracturing system for hard rock

Microwave pre-treatment is considered as a promising technique for alleviating cutter wear. This paper introduces a high-power microwave-induced fracturing system for hard rock. The test system consists of a high-power microwave subsystem (100 kW), a true triaxial testing machine, a dynamic monitoring subsystem, and an electromagnetic shielding subsystem. It can realize rapid microwave-induced fracturing, intelligent tuning of impedance, dynamic feedback under strong microwave fields, and active control of microwave parameters by addressing the following issues: the instability and insecurity of the system, the discharge breakdown between coaxial lines during high-power microwave output, and a lack of feedback of rock-microwave response. In this study, microwave-induced surface and borehole fracturing tests under true triaxial stress were carried out. Experimental comparisons imply that high-power microwave irradiation can reduce the fracturing time of hard rock and that the fracture range (160 mm) of a 915-MHz microwave source is about three times that of 2.45 GHz. After microwave-induced borehole fracturing, many tensile cracks occur on the rock surface and in the borehole: the maximum reduction of the P-wave velocity is 12.8%. The test results show that a high-power microwave source of 915 MHz is more conducive to assisting mechanical rock breaking and destressing. The system can promote the development of microwave-assisted rock breaking equipment.

Impact of amplified spontaneous emission noise on the SRS threshold of high-power fiber amplifiers

Impact of amplified spontaneous emission(ASE)noise on the stimulated Raman scattering(SRS)threshold of highpower fiber amplifiers is demonstrated numerically through a spectral evolution approach.The simulation results confirm that ASE noise in the Raman wavelength band could reduce the SRS threshold of high-power fiber amplifiers significantly.As for ASE noise originated the main amplifier,it becomes stronger and reduces the SRS threshold at shorter operation wavelength below 1052 nm.As for ASE noise originated from the seed laser,it reduces the SRS threshold at different operation wavelength under the condition that the Raman ratio is over-90 dB in the seed laser.The theoretical method and results in this work could provide a well reference to extend the operation wavelength of high-power fiber lasers.

On the Mean Value of High-Powers of a Special Character Sum Modulo a Prime

In this paper,we use the elementary methods,the properties of Dirichlet character sums and the classical Gauss sums to study the estimation of the mean value of high-powers for a special character sum modulo a prime,and derive an exact computational formula.It can be conveniently programmed by the“Mathematica”software,by which we can get the exact results easily.

Analysis of high-power disk laser welding stability based on classification of plume and spatter characteristics

Classification of plume and spatter images was studied to evaluate the welding stability. A high-speed camera was used to capture the instantaneous images of plume and spatters during high power disk laser welding. Characteristic parameters such as the area and number of spatters, the average grayscale of a spatter image, the entropy of a spatter grayscale image, the coordinate ratio of the plume centroid and the welding point, the polar coordinates of the plume centroid were defined and extracted. Karhunen-Loeve transform method was used to change the seven characteristics into three primary characteristics to reduce the dimensions. Also, K-nearest neighbor method was used to classify the plume and spatter images into two categories such as good and poor welding quality. The results show that plume and spatter have a close relationship with the welding stability, and two categories could be recognized effectively using K-nearest neighbor method based on Karhunen-Loeve transform.

Design of Down Scalers in Mixed-Signal GHz Frequency Synthesizer

An optimized method is presented to design the down scalers in a GHz frequency synthesizer. The down scalers are comprised of dual modulus prescaler （DMP） and programmable ＆ pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively. Using a DMP high speed, lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps. The flexibility and reusability of the progrs, mmable divider is high;its use could be extended to many complicated frequency synthesizers. By comparison,it is a better design on performance of high-frequency circuit and good design flexibility.

A 2.4GHz Quadrature Output Frequency Synthesizer

A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator （QVCO） is employed to generate quadrature （I/Q） signals. A second-order loop filter, with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost. The measured spot phase noise is -106.15dBc/Hz@ 1MHz. Close-in phase noise is less than -70dBc/Hz. The synthesizer consumes 13.5mA under a 3.3V voltage supply. The core size is 1.3mm×0. 8mm.

A CMOS Fully Integrated Frequency Synthesizer with Stability Compensation

A complete closed-loop third order s-domain model is analyzed for a frequency synthesizer. Based on the model and root-locus technique, the procedure for parameters design is described, and the relationship between the process,voltage,and temperature variation of parameters and the loop stability is quantitatively analyzed. A variation margin is proposed for stability compensation. Furthermore,a simple adjustable current cell in the charge pump is proposed for additional stability compensation and a novel VCO with linear gain is adopted to limit the total variation. A fully integrated frequency synthesizer from 1 to 1.05GHz with 250kHz channel resolution is implemented to verify the methods.

Frequency synthesizer for DRM/DAB/AM/FM RF front-end

This paper describes a wideband low phase noise frequency synthesizer.It operates in the multi-band including digital radio mondiale DRM digital audio broadcasting DAB amplitude modulation AM and frequency modulation FM .In order to cover the signals of the overall frequencies a novel frequency planning and a new structure are proposed. A wide-band low-phase-noise low-power voltage-control oscillator VCO and a high speed wide band high frequency division ratio pulse swallow frequency divider with a low power consumption are presented.The monolithic DRM/DAB/AM/FM frequency synthesizer chip is also fabricated in a SMIC＇s 0.18-μm CMOS process.The die area is 1 425 μm ×795 μm including the test buffer and pads. The measured results show that the VCO operating frequency range is from 2.22 to 3.57 GHz the measured phase noise of the VCO is 120.22 dBc/Hz at 1 MHz offset the pulse swallow frequency divider operation frequency is from 0.9 to 3.4 GHz.The phase noise in the phase-locked loop PLL is-59.52 dBc/Hz at 10 kHz offset and fits for the demand of the DRM/DAB/AM/FM RF front-end. The proposed frequency synthesizer consumes 47 mW including test buffer under a 1.8 V supply.

Key technologies of frequency-hopping frequency synthesizer for Bluetooth RF front-end

A scheme of a frequency-hopping frequency-synthesizer applied to a Bluetooth ratio frequency （RF） front-end is presented,and design of a voltage controlled oscillator （VCO） and dual-modulus prescaler are focused on.It is fabricated in a 0.18 μm mixed-signal CMOS （complementary metal-oxide-semiconductor transistor） process.The power dissipation of VCO is low and a stable performance is gained.The measured phase noise of VCO at 2.4 GHz is less than -114.32 dBc/Hz.The structure of the DMP is optimized and a novel D-latch integrated with ＂OR＂ logic gate is used.The measured results show that the chip can work well under a 1.8 V power supply.The power dissipation of the core part in a dual modulus prescaler is only 5.76 mW.An RMS jitter of 2 ps is measured on the output signal at 118.3 MHz.It is less than 0.02% of the clock period.

A wideband low-phase-noise LC VCO for DRM/DAB frequency synthesizer

The wideband CMOS voltage-controlled oscillator（VCO）with low phase noise and low power consumption is presented for a DRM/DAB（digital radio mondiale and digital audio broadcasting）frequency synthesizer.In order to obtain a wide band and a large tuning range,a parallel switched capacitor bank is added in the LC tank.The proposed VCO is implemented in SMIC 0.18-μm RF CMOS technology and the chip area is 750 μm×560 μm,including the test buffer circuit and the pads.Measured results show that the tuning range is 44.6%;i.e.,the frequency turning range is from 2.27 to 3.57 GHz.The measured phase noise is-122.22 dBc/Hz at a 1 MHz offset from the carrier.The maximum power consumption of the core part is 6.16 mW at a 1.8 V power supply.

A Novel Method to Compensate the Sigma-Delta Shaped Noise for Wide Band Fractional-N Frequency Synthesizers

A novel method to partially compensate sigma-delta shaped noise is proposed. By injecting the compensation current into the passive loop filter during the delay time of the phase frequency detector（PFD）,a maximum reduction of the phase noise by about 16dB can be achieved. Compared to other compensation methods,the technique proposed here is relatively simple and easy to implement. Key building blocks for realizing the noise cancellation,including the delay variable PFD and compensation current source, are specially designed. Both the behavior level and circuit level simulation results are presented.

A Σ-Δ Fractional-N PLL Frequency Synthesizer with AFC for SRD Applications

A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is adopted to reduce the out-band phase noise. The measurements show a VCO tuning range from 1.31 to 1.88GHz with AFC working correctly,an out-band phase noise of -139dBc/Hz at 3MHz offset frequency, and a fractional spur of less than - 60dBc. The chip area is 1.5mm × 1.2mm and the total current dissipation including LO buffers is 19mA from a single 3.0V supply voltage.

Digital Coarse Tuning Loop for Wide-Band Fast-Settling Dual-Loop Frequency Synthesizers

A new coarse tuning loop for a wide-band dual-loop frequency synthesizer is presented. The coarse tuning structure is composed of two digital modules, including a successive approximation register and a frequency comparator with a novel structure. The frequency comparator counts the prescaler cycles within a certain reference time and compares the number with preset data to estimate the VCO frequency. The frequency comparison error is analyzed in detail. Within a given coarse tuning time,our proposed structure shows a comparison error 20 times smaller than that of other reported structures. This structure also reuses the programmable divider as a part of the coarse tuning loop so that the circuit is greatly simplified.

Three-dimensional simulation method of multipactor in microwave components for high-power space application

Based on the particle-in-cell technology and the secondary electron emission theory, a three-dimensional simulation method for multipactor is presented in this paper. By combining the finite difference time domain method and the panicle tracing method, such an algorithm is self-consistent and accurate since the interaction between electromagnetic fields and particles is properly modeled. In the time domain aspect, the generation of multipactor can be easily visualized, which makes it possible to gain a deeper insight into the physical mechanism of this effect. In addition to the classic secondary electron emission model, the measured practical secondary electron yield is used, which increases the accuracy of the algorithm. In order to validate the method, the impedance transformer and ridge waveguide filter are studied. By analyzing the evolution of the secondaries obtained by our method, multipactor thresholds of these components are estimated, which show good agreement with the experimental results. Furthermore, the most sensitive positions where multipactor occurs are determined from the phase focusing phenomenon, which is very meaningful for multipactor analysis and design.

A 1-GHz Charge Pump PLL Frequency Synthesizer for IEEE 1394b PHY

The design procedure of an 1-GHz phase-locked loop （PLL）-based frequency synthesizer used in IEEE 1394b physical （PHY） system is presented in this paper. The PLL＇s loop dynamics are analyzed in depth and theoretical relationships between all loop parameters are clearly described. All the parameters are derived and verified by Verilog-A model, which ensures the accuracy and efficiency of the circuit design and simulation. A 4-stage ring oscillator is employed to generate 1-GHz oscillation frequency and is divided into low frequency clocks by a feedback divider. The architecture is a third-order, type-2 charge pump PLL. The simulated settling time is less than 4μs. The RMS value of period jitter of the PLL＇s output is 2.1 ps. The PLL core occupies an area of 0.12 mm2, one fourth of which is occupied by the MiM loop capacitors. The total current consumption of the chip is 16.5 mA. The chip has been sent for fabrication in 0.13 μm complementary metal oxide semiconductor （CMOS） technology.

Ti-containing hydrogenated carbon films fabricated by high-power plasma magnetron sputtering

To improve the characteristics of a diamond-like carbon （DLC） film, Ti-containing amorphous hydrogenated carbon thin films were deposited on sus304 stainless steel substrates by high-power plasma-sputtering with titanium metal as the solid plasma source in a mixed ArC2H2 atmosphere. The films were fabricated to obtain a multilayered structure of Ti/TiC/DLC gradient for improving adhesion and reducing residual stress. The effects of substrate bias and target-substrate distance on the films＇ properties were studied by glow discharge spectroscope, X-ray diffractometer, Raman spectroscope, nanoindenter, and a pin-on-disk tribometer. The results indicate that the films possess superior adhesive strength and toughness.

Damage effects and mechanism of the silicon NPN monolithic composite transistor induced by high-power microwaves

A two-dimensional model of the silicon NPN monolithic composite transistor is established for the first time by utilizing the semiconductor device simulator, Sentaurus-TCAD. By analyzing the internal distributions of electric field, current density, and temperature of the device, a detailed investigation on the damage process and mechanism induced by high-power microwaves （HPM） is performed. The results indicate that the temperature elevation occurs in the negative half-period and the temperature drop process is in the positive half-period under the HPM injection from the output port. The damage point is located near the edge of the base-emitter junction of T2, while with the input injection it exists between the base and the emitter of T2. Comparing these two kinds of injection, the input injection is more likely to damage the device than the output injection. The dependences of the damage energy threshold and the damage power threshold causing the device failure on the pulse-width are obtained, and the formulas obtained have the same form as the experimental equations, which demonstrates that more power is required to destroy the device if the pulse-width is shorter. Furthermore, the simulation result in this paper has a good coincidence with the experimental result.

Design and Simulation of High-power LED Array Packaging

Thermal management is one of the key technologies for high-power Light emitting diode(LED)entering into the general illuminating field.Successful thermal management depends on optimal packaging structure and selected packaging materials.In this paper,the aluminum is employed as a substrate of LED,3×3 array chips are placed on the substrate,heat dissipation performance is simulated using finite element analysis(FEA)software,analyzed are the influences on the temperature of the chip with different convection coefficient,and optical properties are simulated using optical analysis software.The results show that the packaging structure can not only effectually improve the thermal performance of high-power LED array but also increase the light extraction efficiency.

Design and high-power test of 800-kW UHF klystron for CEPC

To reduce the energy demand and operation cost for circular electron positron collider(CEPC), the high efficiency klystrons are being developed at Institute of High Energy Physics, Chinese Academy of Sciences. A 800-k W continuous wave(CW) klystron operating at frequency of 650-MHz has been designed. The results of beam–wave interaction simulation with several different codes are presented. The efficiency is optimized to be 65% with a second harmonic cavity in three-dimensional(3D) particle-in-cell code CST. The effect of cavity frequency error and mismatch load on efficiency of klystron have been investigated. The design and cold test of reentrant cavities are described, which meet the requirements of RF section design. So far, the manufacturing and high-power test of the first klystron prototype have been completed.When the gun operated at DC voltage of 80 k V and current of 15.4 A, the klystron peak power reached 804 k W with output efficiency of about 65.3% at 40% duty cycle. The 1-d B bandwidth is ±0.8 MHZ. Due to the crack of ceramic window, the CW power achieved about 700 kW. The high-power test results are in good agreement with 3D simulation.