Non-PLL high-precision synchronous sampling method among lots of acoustics acquisition channels for underwater multilinear array seismic exploration system

Synchronous sampling is very essential in underwater multilinear array seismic exploration system in which every acquisition node(AN)samples analog signals by its own analog-digital converter(ADC).Aiming at the problems of complex synchronous sampling method and long locking time after varying sampling rate in traditional underwater seismic exploration system,an improved synchronous sampling model based on the master-slave synchronous model and local clock asynchronous drive with non phase locked loop(PLL)is built,and a high-precision synchronous sampling method is proposed,which combines the short-term stability of local asynchronous driving clock with the master-slave synchronous calibration of local sampling clock.Based on the improved synchronous sampling model,the influence of clock stability,transmission delay and phase jitter on synchronous sampling error is analyzed,and a high-precision calibration method of synchronous sampling error based on step-by-step compensation of transmission delay is proposed.The model and method effectively realize the immunity of phase jitter on synchronous sampling error in principle,and compensate the influence of signal transmission delay on synchronous sampling error.At the same time,it greatly reduces the complexity of software and hardware implementation of synchronous sampling,and solves the problem of long locking time after changing the sampling rate in traditional methods.The experimental system of synchronous sampling for dual linear array is built,and the synchronous sampling accuracy is better than 5 ns.

MEMS Huygens Clock Based on Synchronized Micromechanical Resonators

With the continuous miniaturization of electronic devices,microelectromechanical system(MEMS)oscillators that can be combined with integrated circuits have attracted increasing attention.This study reports a MEMS Huygens clock based on the synchronization principle,comprising two synchronized MEMS oscillators and a frequency compensation system.The MEMS Huygens clock improved shorttime stability,improving the Allan deviation by a factor of 3.73 from 19.3 to 5.17 ppb at 1 s.A frequency compensation system based on the MEMS oscillator’s temperature-frequency characteristics was developed to compensate for the frequency shift of the MEMS Huygens clock by controlling the resonator current.This effectively improved the long-term stability of the oscillator,with the Allan deviation improving by 1.6343105 times to 30.9 ppt at 6000 s.The power consumption for compensating both oscillators simultaneously is only 2.85 mW·℃^(-1).Our comprehensive solution scheme provides a novel and precise engineering solution for achieving high-precision MEMS oscillators and extends synchronization applications in MEMS.

Proposal for a realtime Einstein-synchronization-defined satellite virtual clock

Realization of high performance satellite onboard clock is vital for various positioning, navigation, and timing applications. For further improvement of the synchronization-based satellite time and frequency references, we propose a geosynchronous(GEO) satellite virtual clock concept based on ground–satellite synchronization and present a beacon transponder structure for its implementation(scheduled for launch in 2025), which does not require atomic clocks to be mounted on the satellite. Its high performance relies only on minor modifications to the existing transponder structure of GEO satellites. We carefully model the carrier phase link and analyze the factors causing link asymmetry within the special relativity. Considering that performance of such synchronization-based satellite clocks is primarily limited by the link's random phase noise, which cannot be adequately modeled, we design a closed-loop experiment based on commercial GEO satellites for pre-evaluation. This experiment aims at extracting the zero-means random part of the ground-satellite Ku-band carrier phase via a feedback loop. Ultimately, we obtain a 1σ value of 0.633 ps(two-way link), following the Gaussian distribution. From this result, we conclude that the proposed real-time Einstein-synchronization-defined satellite virtual clock can achieve picosecond-level replication of onboard time and frequency.

Einstein’s Concept of Clock Synchronization Conflicts with the Second Relativity Postulate

Einstein defined clock synchronization whenever photon pulses with timetags traverse a fixed distance between two clocks with equal time spans ineither direction. Using the second relativity postulate, he found clocksmounted on a rod uniformly moving parallel with the rod’s length cannot besynchronized, but clocks attached to a stationary rod can. He dismissed thisdiscrepancy by claiming simultaneity and clock synchronization were not commonbetween inertial frames, but this paper proves with both Galilean and Lorentztransformations that simultaneity and clock synchronization are preservedbetween inertial frames. His derivation means moving clocks can never besynchronized in a “resting” inertial frame. Ultraprecise atomic clocks intimekeeping labs daily contradict his results. No algebraic error occurred inEinstein’s derivations. The two cases of clocksattached to a rod reveal three major conflicts with the currentsecond postulate. The net velocity between a photon source and detector plusthe “universal” velocity c is mathematically equivalent toEinstein’s clock synchronization method. As the ultraprecise timekeepingcommunity daily synchronizes atomic clocks on the moving Earth withultraprecise time uncertainty well below Einstein’s lowest limit ofsynchronization, the theoretical resolution of the apparent conflict isaccomplished by expanding the second relativity postulate to incorporate thenet velocity between the photon source and detector with the emitted velocity c as components of the total velocity c. This means the magnitudeof the total photon velocity can exceed the speed limit (299792458 m/s) set by the standard velocity c. .

New Synchronization Algorithm and Analysis of Its Convergence Rate for Clock Oscillators in Dynamical Network with Time-Delays

New synchronization algorithm and analysis of its convergence rate for clock oscillators in dynamical network with time-delays are presented.A network of nodes equipped with hardware clock oscillators with bounded drift is considered.Firstly,a dynamic synchronization algorithm based on consensus control strategy,namely fast averaging synchronization algorithm （FASA）,is presented to find the solutions to the synchronization problem.By FASA,each node computes the logical clock value based on its value of hardware clock and message exchange.The goal is to synchronize all the nodes＇ logical clocks as closely as possible.Secondly,the convergence rate of FASA is analyzed that proves it is related to the bound by a nondecreasing function of the uncertainty in message delay and network parameters.Then,FASA＇s convergence rate is proven by means of the robust optimal design.Meanwhile,several practical applications for FASA,especially the application to inverse global positioning system （IGPS） base station network are discussed.Finally,numerical simulation results demonstrate the correctness and efficiency of the proposed FASA.Compared FASA with traditional clock synchronization algorithms （CSAs）,the convergence rate of the proposed algorithm converges faster than that of the CSAs evidently.

A clock synchronization method based on IEEE 1588 and its implementation on Ethernet

We presented a clock synchronization method that contained a clock adjusting algorithm and a frequency compensated clock to achieve precise synchronization among distributed clocks based on IEEE 1588 protocol.Further,we presented its application on Ethernet and implementation of the frequency compensated clock in a field programmable gate array(FPGA) as experiments.The results indicate that this method can support sub-microsecond synchronization with inexpensive standard crystal oscillators.

Clock synchronization design and evaluation for trigger-less data acquisition system

For modern particle physics experiments,trigger-less data acquisition(DAQ) system has been put into practice because of the need of reaction multiplicity and trigger flexibility.In such new DAQ systems,global synchronized clock plays an important role because it affects the granularity of time slice and precision of reference clock.In this paper,a novel synchronized clock distribution method is proposed.With the help of modulation technique,master clock module distributes system clock to each slave module.To synchronize slave clocks,the propagation delay is adjusted and the clock phase is aligned by an FPGA chip automatically.Furthermore,an ADCbased method is proposed to evaluate the performance of multi-module clock synchronization simultaneously.The experiments of a prototype system show that slave clocks can be synchronized less than 100 ps over 150 m range.The proposed method is simple and flexible,and it can be used in trigger-less DAQ system and other applications of clock distribution preciously.

Modelling of intercellular synchronization in the Drosophila circadian clock

In circadian rhythm generation, intercellular signaling factors are shown to play a crucial role in both sustaining intrinsic cellular rhythmicity and acquiring collective behaviours across a population of circadian neurons. However, the physical mechanism behind their role remains to be fully understood. In this paper, we propose an indirectly coupled multicellular model for the synchronization of Drosophila circadian oscillators combining both intracellular and intercellular dynamics. By simulating different experimental conditions, we find that such an indirect coupling way can synchronize both heterogeneous self-sustained circadian neurons and heterogeneous mutational damped circadian neurons. Moreover, they can also be entrained to ambient light-dark （LD） cycles depending on intercellular signaling.

A scheme for implementing quantum clock synchronization algorithm in cavity QED

In this paper, we propose a scheme for implementing the quantum clock synchronization （QCS） algorithm in cavity quantum electrodynamic （QED） formalism. Our method is based on three-level lader-type atoms interacting with classical and quantized cavity fields. Atom-qubit realizations of three-qubit and four-qubit QCS algorithms are explicitly presented.

Iterative quantum algorithm for distributed clock synchronization

Clock synchronization is a well-studied problem with many practical and scientific applications.We propose an arbitrary accuracy iterative quantum algorithm for distributed clock synchronization using only three qubits.The n bits of the time difference between two spatially separated clocks can be deterministically extracted by communicating only O（n） messages and executing the quantum iteration process n times based on the classical feedback and measurement operations.Finally,we also give the algorithm using only two qubits and discuss the success probability of the algorithm.

Heuristics Scheduling Algorithm on the Links Scheduling of Satellite-Ground Clock Synchronization and Ephemeris Uploading in COMPASS System

The execution process of satellite-ground clock synchronization and ephemeris uploading in the system is analyzed,as well as their characterized operation and their relationship.Based on the analysis of the scheduling goal and constraint character,a heuristics rule-based multi-stage link scheduling algorithm was put forward.The algorithm distinguishes the on-off-frontier satellites from the others and schedules them by turns.The paper presented the main flow as well as the detailed design of the rule.Finally based on the current COMPASS global system,some typical resources and constraints are selected to generate an instance.Then the comparison analysis between the heuristics scheduling algorithm and three other traditional scheduling strategies are carried out.The result shows the validity and reasonability of the multi-stage strategy.

Scalable Clock Synchronization Analysis:A Symmetric Noncooperative Output Feedback Tubes-MPC Approach

In the cyber-physical environment,the clock synchronization algorithm is required to have better expansion for network scale.In this paper,a new measurement model of observability under the equivalent transformation of minimum mean square error(MMSE)is constructed based on basic measurement unit(BMU),which can realize the scaled expansion of MMSE measurement.Based on the state updating equation of absolute clock and the decoupled measurement model of MMSElike equivalence,which is proposed to calculate the positive definite invariant set by using the theoretical-practical Luenberger observer as the synthetical observer,the local noncooperative optimal control problem is built,and the clock synchronization system driven by the ideal state of local clock can reach the exponential convergence for synchronization performance.Different from the problem of general linear system regulators,the state estimation error and state control error are analyzed in the established affine system based on the set-theoryin-control to achieve the quantification of state deviation caused by noise interference.Based on the BMU for isomorphic state map,the synchronization performance of clock states between multiple sets of representative nodes is evaluated,and the scale of evaluated system can be still expanded.After the synchronization is completed,the state of perturbation system remains in the maximum range of measurement accuracy,and the state of nominal system can be stabilized at the ideal state for local clock and realizes the exponential convergence of the clock synchronization system.

Maximum Likelihood Estimation of Clock Synchronization Error in OFDM System

The performance degradation of an orthogonal frequency division multiplexing (OFDM) systems due to clock synchronization error is analyzed and a pilot-aided maximum likelihood (ML) estimating method is proposed to correct it. The proposed algorithm enables clock synchronization error estimation from a pilot whose duration is only two symbol periods. The study shows that this method is simple and exact. The clock synchronization error can be corrected almost entirely.

同步电路设计中CLOCK SKEW的分析

Clock skew是数字集成电路设计中一个重要的因素。本文比较了在同步电路设计中 0 clock skew和非 0clock skew时钟分布对电路性能的影响 ,分析了通过调整时钟树中 CL OCK SKEW来改善电路性能的方法 ,从而说明非 0 clock skew时钟分布是如何提高同步电路运行的最大时钟频率的。

Distributed Time Synchronization in Wireless Sensor Networks via Second-Order Consensus Algorithms

This paper proposes a distributed second-order consensus time synchronization, which incorporates the second-order consensus algorithm into wireless sensor networks. Since local clocks may have different skews and offsets, the algorithm is designed to include offset compensation and skew compensation. The local clocks are not directly modified, thus the virtual clocks are built according to the local clocks via the compensation parameters. Each node achieves a virtual consensus clock by periodically updated compensation parameters. Finally, the effectiveness of the proposed algorithm is verified through a number of simulations in a mesh network. It is proved that the proposed algorithm has the advantage of being distributed, asymptotic convergence, and robust to new node joining.

The Importance of Time Synchronization in the Local Networks of the Science and Application Center for Lunar and Deep-space Exploration

The data acquisition stations and the data processing center of the Science and Application Center for Lunar and Deep-space Exploration (SACLuDE) are located at different geographical sites. They respectively have their own local networks and interconnect with each other through access to the core data network. This paper describes the clock drift in the computer and other networked devices building up the infrastructure of the above local networks. The network time variance of the stochastic model is also estimated. The poor precision of network synchronization will bring about potential hazards to the network operation and application running in the networks, which is clarified in the present paper. At the end of the paper, a cost-effective and feasible solution is proposed based on the Global Position System (GPS) and the Network Time Protocol (NTP).

A high-precision synchronization circuit for clock distribution

In this paper, a novel structure of a high-precision synchronization circuit, HPSC, using interleaved delay units and a dynamic compensation circuit is proposed. HPSCs are designed for synchronization of clock distribution networks in large-scale integrated circuits, where high-quality clocks are required. The application of a hybrid structure of a coarse delay line and dynamic compensation circuit performs roughly the alignment of the clock signal in two clock cycles, and finishes the fine tuning in the next three clock cycles with the phase error suppressed under 3.8 ps. The proposed circuit is implemented and fabricated using a SMIC 0.13 μm 1P6M process with a supply voltage at 1.2 V. The allowed operation frequency ranges from 200 to 800 MHz, and the duty cycle ranges between [20%, 80%]. The active area of the core circuits is 245 × 134 μm2, and the power consumption is 1.64 mW at 500 MHz.

A new synchronization scheme based on time division multiplexing and wavelength division multiplexing technology for practical quantum key distribution system

Three clock synchronization schemes for a quantum key distribution system are compared experimentally through the outdoor fibre and the interaction physical model of the the clock signal and the the quantum signal in the quantum key distribution system is analysed to propose a new synchronization scheme based on time division multiplexing and wavelength division multiplexing technology to reduce quantum bits error rates under some transmission rate conditions, The proposed synchronization scheme can not only completely eliminate noise photons from the bright background light of the the clock signal, but also suppress the fibre nonlinear crosstalk.

A method for measuring the clock offset of two hosts in the network

In order to detect the performance parameters of the network, for example, the network delay or delay jitter, the clock synchronization relations between the two hosts at two ends along the network must be calculated in advance. Then with the correct temporal relations between the two hosts, multimedia transmission along the network and display can occur by the proper order. A refined method based on Paxson's algorithm is proposed and testified. More accurate results can be attained by the method. By the way, the method can be used in a more complicated environment. Furthermore, an end-to-end network performance tester based on the proposed algorithm is designed and implemented.