A novel ASIC design of changeable-point digital pulse compression (DPC) chip is presented. System hardware resource is reduced to one third of the traditional design method through operations sharing hardware, (i.e.) ...A novel ASIC design of changeable-point digital pulse compression (DPC) chip is presented. System hardware resource is reduced to one third of the traditional design method through operations sharing hardware, (i.e.) let FFT, complex multiplication and IFFT be fulfilled with the same hardware structure. Block-floating-point scaling is used to enhance the dynamic range and computation accuracy. This design applies parallel pipeline structure and the radix-4 butterfly operation to improve the processing speed. In addition, a triple-memory-space(TMS) configuration is used that allows input, computation and output operations to be overlapped, so that the dual-butterfly unit is never left in an idle state waiting for I/O operation. The whole design is implemented with only one chip of XC2V500-5 FPGA. It can implement 1 024-point DPC within 91 6 μs.The output data is converted to floating-point formation to achieve seamless interface with TMS320C6701. The validity of the design is verified by simulation and measurement results.展开更多
This paper describes a pulse compressor implementation with DSP for small Time Bandwidth (TB) product Linear Frequency Modulation (LFM) waveform. It contains the digital generation of the LFM waveform and the dig...This paper describes a pulse compressor implementation with DSP for small Time Bandwidth (TB) product Linear Frequency Modulation (LFM) waveform. It contains the digital generation of the LFM waveform and the digital internally Hamming weighted compression filter. Two methods for suppression of time sidelobe of the digital pulse compressor are employed. First, the LFM waveform is modified by using cubic phase pre distortion for reducing the effect of Fresnel ripples in small TB product LFM waveform. Secondly, anti aliasing filter is used before A/D converter for reducing spectrum skirt level of the returned LFM waveform. The parameters of the compression filter implemented with IMSA100 DSP are programmable. The experiments show that the peak time sidelobe level of the digital pulse compressor is less than -32 dB for TB product of 20.展开更多
提出了将射频直接采样数字化的接收方式应用于数字电离层测高仪系统的设计方案,并详细介绍了该方案在CAS-DIS(Chinese Academy of Sciences,Digital Ionosonde)电离层测高仪系统的应用,给出了CAS-DIS电离层测高仪在中国武汉电离层探测...提出了将射频直接采样数字化的接收方式应用于数字电离层测高仪系统的设计方案,并详细介绍了该方案在CAS-DIS(Chinese Academy of Sciences,Digital Ionosonde)电离层测高仪系统的应用,给出了CAS-DIS电离层测高仪在中国武汉电离层探测标校试验场和武汉-北京斜向电离层探测系统中的实验结果.观测结果表明,采用本文提出的数字化方案设计的电离层测高仪系统性能优越,且可以分别工作在垂直和斜向探测模式,满足了电离层探测的多种应用需求.展开更多
介绍了直接数字波形合成(direct digital waveform synthesizer,DDWS)的误差来源,分析了DDWS结构中其数模转换器(DAC)信号重构机理,比较研究了DAC信号重构误差对输出信号脉冲压缩结果的影响。提出了一种针对DAC带来的信号辛格函数调制...介绍了直接数字波形合成(direct digital waveform synthesizer,DDWS)的误差来源,分析了DDWS结构中其数模转换器(DAC)信号重构机理,比较研究了DAC信号重构误差对输出信号脉冲压缩结果的影响。提出了一种针对DAC带来的信号辛格函数调制误差的数字化补偿算法,对中频30 MHz,带宽分别为40 MHz和20 MHz的超宽带低中频线性调频信号进行了实际补偿。实验结果表明该算法简单方便,能有效补偿DAC带来的波形调制误差。展开更多
文摘A novel ASIC design of changeable-point digital pulse compression (DPC) chip is presented. System hardware resource is reduced to one third of the traditional design method through operations sharing hardware, (i.e.) let FFT, complex multiplication and IFFT be fulfilled with the same hardware structure. Block-floating-point scaling is used to enhance the dynamic range and computation accuracy. This design applies parallel pipeline structure and the radix-4 butterfly operation to improve the processing speed. In addition, a triple-memory-space(TMS) configuration is used that allows input, computation and output operations to be overlapped, so that the dual-butterfly unit is never left in an idle state waiting for I/O operation. The whole design is implemented with only one chip of XC2V500-5 FPGA. It can implement 1 024-point DPC within 91 6 μs.The output data is converted to floating-point formation to achieve seamless interface with TMS320C6701. The validity of the design is verified by simulation and measurement results.
文摘This paper describes a pulse compressor implementation with DSP for small Time Bandwidth (TB) product Linear Frequency Modulation (LFM) waveform. It contains the digital generation of the LFM waveform and the digital internally Hamming weighted compression filter. Two methods for suppression of time sidelobe of the digital pulse compressor are employed. First, the LFM waveform is modified by using cubic phase pre distortion for reducing the effect of Fresnel ripples in small TB product LFM waveform. Secondly, anti aliasing filter is used before A/D converter for reducing spectrum skirt level of the returned LFM waveform. The parameters of the compression filter implemented with IMSA100 DSP are programmable. The experiments show that the peak time sidelobe level of the digital pulse compressor is less than -32 dB for TB product of 20.
文摘提出了将射频直接采样数字化的接收方式应用于数字电离层测高仪系统的设计方案,并详细介绍了该方案在CAS-DIS(Chinese Academy of Sciences,Digital Ionosonde)电离层测高仪系统的应用,给出了CAS-DIS电离层测高仪在中国武汉电离层探测标校试验场和武汉-北京斜向电离层探测系统中的实验结果.观测结果表明,采用本文提出的数字化方案设计的电离层测高仪系统性能优越,且可以分别工作在垂直和斜向探测模式,满足了电离层探测的多种应用需求.
