ANALYSIS OF THE TRANSMISSION PROPERTIES OF TAPERED MUTLICONDUCTOR INTERCONNECTING BUSES IN HIGH-SPEED INTEGRATED CIRCUITS

Analysis approach and formulas for the transmission properties of uniform multicon-ductor interconnecting buses in high-speed integrated circuits are presented in this article. And further, by using a network approach, a tapered bus system can be analyzed as a set of cascaded uniform buses with slightly different strip widths. Obtained results are in good agreement with the experimental data.

Power supply arm protection scheme of high-speed railway based on wide-area current differential

When fault occurs on cross-coupling autotransformer(AT)power supply traction network,the up-line and down-line feeder circuit breakers in the traction substation trip at the same time without selectivity,which leads to an extended power failure.Based on equivalent circuit and Kirchhoff’s current law,the feeder current characteristic in the substation,AT station and sectioning post when T-R fault,F-R fault,and T-F fault occur are analyzed and their expressions are obtained.When the traction power supply system is equipped with wide-area protection measurement and control system,the feeder protection device in each station collects the feeder currents in other two stations through the wide-area protection channel and a wide-area current differential protection scheme based on the feeder current characteristic is proposed.When a short-circuit fault occurs in the power supply arm,all the feeder protection devices in each station receive the feeder currents with time stamp in other two stations.After data synchronous processing and logic judgment,the fault line of the power supply arm can be identified and isolated quickly.The simulation result based on MATLAB/Simulink shows that the power supply arm protection scheme based on wide-area current differential has good fault discrimination ability under different fault positions,transition resistances,and fault types.The verification of measured data shows that the novel protection scheme will not be affected by the special working conditions of the electrical multiple unit(EMU),and reliability,selectivity,and rapidity of relay protection are all improved.

Electromagnetic Analysis and Optimization of High-speed Maglev Linear Synchronous Motor Based on Field-circuit Coupling

High speed maglev train has become a new non-contact transportation mode mainly studied in recent years because of its non-sticking and high speed characteristics.Firstly,the finite element model of the long stator linear synchronous motor(LSM)is established based on the structure of the test prototype.After calculation,it is compared with the experimental data and verified.On this basis,a field-circuit coupling model based on inverter circuit is established,and the influence of carrier wave ratio change on the output characteristics of LSM is calculated and analyzed.Finally,the filter circuit is introduced into the field-circuit coupling model,and the influence of the filter circuit on the output characteristics of the LSM is compared and analyzed.

Sensitivity analysis of distributed parameter elements in high-speed circuit networks

This paper presents an analysis method, based on MacCormack＇s technique, for the evaluation of the time domain sensitivity of distributed parameter elements in high-speed circuit networks. Sensitivities can be calculated from electrical and physical parameters of the distributed parameter elements. The proposed method is a direct numerical method of time-space discretization and does not require complicated mathematical deductive process. Therefore, it is very convenient to program this method. It can be applied to sensitivity analysis of general transmission lines in linear or nonlinear circuit networks. The proposed method is second-order-accurate. Numerical experiment is presented to demonstrate its accuracy and efficiency.

Analysis of Temperature Rise in High-Speed Permanent Magnet Synchronous Traction Motors by Coupling the Equivalent Thermal Circuit Method and Computational Fluid Dynamics

To solve the problem of temperature rise caused by the high power density of high-speed permanent magnet synchronous traction motors,the temperature rise of various components in the motor is analyzed by coupling the equivalent thermal circuit method and computational fluid dynamics.Also,a cooling strategy is proposed to solve the problem of temperature rise,which is expected to prolong the service life of these devices.First,the theoretical bases of the approaches used to study heat transfer and fluid mechanics are discussed,then the fluid flow for the considered motor is analyzed,and the equivalent thermal circuit method is introduced for the calculation of the temperature rise.Finally,the stator,rotor loss,motor temperature rise,and the proposed cooling method are also explored through experiments.According to the results,the stator temperature at 50,000 r/min and 60,000 r/min at no-load operation is 68℃ and 76℃,respectively.By monitoring the temperature of the air outlets inside and outside the motor at different speeds,it is also found that the motor reaches a stable temperature rise after 65 min of operation.Coupling of the thermal circuit method and computational fluid dynamics is a strategy that can provide the average temperature rise of each component and can also comprehensively calculate the temperature of each local point.We conclude that a hybrid cooling strategy based on axial air cooling of the inner air duct of the motor and water cooling of the stator can meet the design requirements for the ventilation and cooling of this type of motors.

BALANCED TRUNCATED MODELS OF C INTERCONNECT CIRCUITS AND THEIR SIMULATION

The Balanced Truncation Method (BTM) is applied to an even distributed RC interconnect case by using Wang's closed-forms of even distributed RC interconnect models. The results show that extremely high order RC interconnect can be high-accurately approximated by only third order balanced model. Related simulations are executed in both time domain and frequency domain. The results may be applied to VLSI interconnect model reduction and design.

Review of the Global Trend of Interconnect Reliability for Integrated Circuit

Interconnect reliability has been regarded as a discipline that must be seriously taken into account from the early design phase of integrated circuit (IC). In order to study the status and trend of the interconnect reliability, a comprehensive review of the published literatures is carried out. This can depict the global trend of ICs’ interconnect reliability and help the new entrants to understand the present situation of this area.

Unraveling complexity of interconnected regulatory circuits in lipid metabolism

In this issue of Journal of Biomedical Research,3review articles are published that cover a broad range of topics addressing current understanding on regulation of nutrient metabolism through protein phosphatases,homeostatic regulation of cellular lipid droplets by small GTPases,and mechanisms by which hepatic assembly and secretion of triglyceride-rich lipoproteins are regulated.

某型号导引头电子组件柔性互连技术研究

导引头系列产品中,非规则线缆的广泛应用、大批量需求及纯手工制作的生产特点,已满足不了导引头生产装配的自动化发展需求。针对导引头系列产品的小型化、轻量化、集成化发展趋势,需要一种新型电气互连方式来解决产品生产过程中非规则线缆制作这一瓶颈问题。利用电子组件柔性互连技术,采用刚柔结合印制板制造形式,实现了电信号在导引头内的稳定传输与可靠连接,经过抗载验证,满足了导引头抗载应用需求,达到了导引头非规则线缆自动化、批量化制作的目的。

硅基集成光开关阵列的高速驱动控制电路设计

通过分析光开关单元的物理结构,提出等效电学模型,用于模拟光开关单元的瞬态响应.基于该模型,针对光开关阵列设计高速驱动控制电路,结合仿真探究电压尖峰对光开关单元瞬态响应的影响.系统测试结果表明,驱动电路施加的电压信号的上升/下降时间为1.7/1.6 ns,能够满足高速光开关纳秒级切换速度的需求.在该驱动电路的配合下,光开关阵列的切换时间为2.1~5.9 ns,实现了较先进的高速光交换系统.

高精度集成感应电路互连技术研究

文章通过建立微盲孔填铜模型、刚性电路板高厚径比和挠性电路板通孔电镀铜模型,同时基于电化学测试结果进行电镀铜的数值模拟计算,对镀液对流对浓度边界层的影响、加速剂在电极表面的积累效应、镀层均匀性、镀槽内电场分布和添加剂作用机制等进行了分析。通过设计印制电路图形,对图形电镀镀层均匀性影响因素进行分析,以此确定最优工艺和参数;达到电镀铜表面同层厚度的均匀性与填铜的平整性效果,从而达到了减小盲孔孔径直径,降低孔深、铜层、面铜厚度和抗蚀膜厚度的目的。通过研究,文章实现了高密度互连印制电路板线路的微细化,达到了电气互连孔更小、密度更高,可靠性和感应程度更强的效果。

半挠性高精密互联印制板加工技术研究

文章主要介绍了一款2阶叠孔高密度互连(HDI)半挠性印制板,此款产品集不对称压合、电镀填孔、揭盖等特点,且各层次芯板底铜厚度不同,需经多次减铜流程,严格控制面铜厚度,以保证最小线宽精度,产品集HDI和半挠性印制板特性于一身,有一定的制作难度。通过制作前识别产品制作过程中重点和难点,对关键技术进行优化,有效保证了产品的质量。

集成电路有机基板倒装焊失效分析与改善

为了满足产品便携化和多功能化的需求,芯片设计正朝着多功能和大规模集成的趋势发展,集成电路封装也逐步向大尺寸、高密度的方向演进,特别是倒装芯片技术的应用,可以实现更高的封装密度和更快的信号传输速度。然而,不同材料的热膨胀系数存在差异,热失配容易引发互联凸点开路失效。为研究有机基板倒装焊集成电路在封装制程中失效的原因,采用扫描电子显微镜(SEM)结合有限元分析法,模拟有机基板在温度循环和回流焊过程中的应力分布状态并进行分析,结果表明,在回流焊过程中有机基板四周边缘位置的凸点所受应力较大。采用磁性载具和在焊盘上预制焊料的方法可以显著降低电路失效风险。

Implementation of low-swing differential interface circuits for high-speed on-chip asynchronous interconnection

A novel low-swing interface circuit for high-speed on-chip asynchronous interconnection is proposed in this paper. It takes a differential level-triggered latch to recover digital signal with ultra low-swing voltage less than 50 mV, and the driver part of the interface circuit is optimized for low power using the driver-array method, With a capacity to work up to 500 MHz, the proposed circuit, which is simulated and fabricated using SMIC 0.18-pm 1.8-V digital CMOS technology, consumes less power than previously reported designs.

An interconnect width and spacing optimization model considering scattering effect

As the feature size of the CMOS integrated circuit continues to shrink, the more and more serious scattering effect has a serious impact on interconnection performance, such as delay and bandwidth. Based on the impact of the scattering effect on latency and bandwidth, this paper first presents the quality-factor model which optimises latency and bandwidth effectively with the consideration of the scattering effect. Then we obtain the analytical model of line width and spacing with application of curve-fitting method. The proposed model has been verified and compared based on the nano-scale CMOS technology. This optimisation model algorithm is simple and can be applied to the interconnection system optimal design of nano-scale integrated circuits.

Weighted Self-Adaptive Threshold Wavelets for Interpolation Point Selection Used in Interconnect MOR

As process technology development,model order reduction( MOR) has been regarded as a useful tool in analysis of on-chip interconnects. We propose a weighted self-adaptive threshold wavelet interpolation MOR method on account of Krylov subspace techniques. The interpolation points are selected by Haar wavelet using weighted self-adaptive threshold methods dynamically. Through the analyses of different types of circuits in very large scale integration( VLSI),the results show that the method proposed in this paper can be more accurate and efficient than Krylov subspace method of multi-shift expansion point using Haar wavelet that are no weighted self-adaptive threshold application in interest frequency range,and more accurate than Krylov subspace method of multi-shift expansion point based on the uniform interpolation point.

A novel low-swing interconnect optimization model with delay and bandwidth constraints

Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits. Based on the RLC interconnect delay model, by wire sizing, wire spacing arid adopting low-swing interconnect technology, this paper proposed a power-area optimization model considering delay and bandwidth constraints simultaneously. The optimized model is verified based on 65-am and 90-nm complementary metal-oxide semiconductor （CMOS） interconnect parameters. The verified results show that averages of 36% of interconnect power and 26% of repeater area can be saved under 65-nm CMOS process. The proposed model is especially suitable for the computer-aided design of nanometer scale systems-on-chip.

TRANSIENT ANALYSIS OF TRANSMISSION LINE CIRCUITS BASED ON THE SEMIDISCRETIZATION OF TELEGRAPH EQUATIONS

A new transient analysis method for the transmission line circuits is presented in this paper. Based on the semidiscretization of the telegraph equations, a discretized time domain companion models for the transmission lines which can be conveniently implemented in a general circuit simulator such as SPICE is derived. The computation required for the model is linear with time, equivalent to the recursive convolution-based method. The formulations for both single and coupled lossy transmission lines are given. Numerical experiments are carried out to demonstrate the validity of the method.

Current sustainability and electromigration of Pd,Sc and Y thin-films as potential interconnects

The progress on novel interconnects for carbon nanotube(CNT)-based electronic circuit is by far behind the remarkable development of CNT-field effect transistors.The Cu interconnect material used in current integrated circuits seems not applicable for the novel interconnects,as it requires electrochemical deposition followed by chemical-mechanical polishing.We report our experimental results on the failure current density,resistivity,electromigration effect and failure mechanism of patterned stripes of Pd,Sc and Y thin-films,regarding them as the potential novel interconnects.The Pd stripes have a failure current density of(8~10)×106 A/cm^2(MA/cm^2),and they are stable when the working current density is as much as 90% of the failure current density.However,they show a resistivity around 210 μΩ·cm,which is 20 times of the bulk value and leaving room for improvement.Compared to Pd,the Sc stripes have a similar resistivity but smaller failure current density of 4~5 MA/cm^2.Y stripes seem not suitable for interconnects by showing even lower failure current density than that of Sc and evidence of oxidation.For comparison,Au stripes of the same dimensions show a failure current density of 30 MA/cm^2 and a resistivity around 4 μΩ·cm,making them also a good material as novel interconnects.