Mobility enhancement of strained GaSb p-channel metal-oxide-semiconductor field-effect transistors with biaxial compressive strain

Various biaxial compressive strained GaSb p-channel metal-oxide-semiconductor field-effect transistors （MOSFETs） are experimentally and theoretically investigated, The biaxial compressive strained GaSb MOSFETs show a high peak mobility of 638 cm2/V.s, which is 3.86 times of the extracted mobility of the fabricated GaSb MOSFETs without strain. Meanwhile, first principles calculations show that the hole effective mass of GaSb depends on the biaxial compressive strain. The biaxiai compressive strain brings a remarkable enhancement of the hole mobility caused by a significant reduction in the hole effective mass due to the modulation of the valence bands.

Modeling electric field of power metal-oxide-semiconductor field-effect transistor with dielectric trench based on Schwarz–Christoffel transformation

A power metal-oxide-semiconductor field-effect transistor(MOSFET) with dielectric trench is investigated to enhance the reversed blocking capability. The dielectric trench with a low permittivity to reduce the electric field at reversed blocking state has been studied. To analyze the electric field, the drift region is segmented into four regions, where the conformal mapping method based on Schwarz–Christoffel transformation has been applied. According to the analysis, the improvement in the electric field for using the low permittivity trench is mainly due to the two electric field peaks generated in the drift region around this dielectric trench. The analytical results of the electric field and the potential models are in good agreement with the simulation results.

Effect of depositing PCBM on perovskite-based metal–oxide–semiconductor field effect transistors

In this manuscript,the perovskite-based metal–oxide–semiconductor field effect transistors（MOSFETs） with phenylC61-butyric acid methylester（PCBM） layers are studied.The MOSFETs are fabricated on perovskites,and characterized by photoluminescence spectra（PL）,x-ray diffraction（XRD）,and x-ray photoelectron spectroscopy（XPS）.With PCBM layers,the current–voltage hysteresis phenomenon is effetely inhibited,and both the transfer and output current values increase.The band energy diagrams are proposed,which indicate that the electrons are transferred into the PCBM layer,resulting in the increase of photocurrent.The electron mobility and hole mobility are extracted from the transfer curves,which are about one order of magnitude as large as those of PCBM deposited,which is the reason why the electrons are transferred into the PCBM layer and the holes are still in the perovskites,and the effects of ionized impurity scattering on carrier transport become smaller.

Evaluation of a gate-first process for AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors with low ohmic annealing temperature

In this paper, TiN/A1Ox gated A1GaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors （MOS- HFETs） were fabricated for gate-first process evaluation. By employing a low temperature ohmic process, ohmic contact can be obtained by annealing at 600 ℃ with the contact resistance approximately 1.6 Ω.mm. The ohmic annealing process also acts as a post-deposition annealing on the oxide film, resulting in good device performance. Those results demonstrated that the TiN/A1Ox gated MOS-HFETs with low temperature ohmic process can be applied for self-aligned gate AIGaN/GaN MOS-HFETs.

Fabrication and characterization of the normally-off N-channel lateral 4H–SiC metal–oxide–semiconductor field-effect transistors

In this paper, the normally-off N-channel lateral 4H-SiC metal-oxide-semiconductor field-effect transistors （MOSF- FETs） have been fabricated and characterized. A sandwich- （nitridation-oxidation-nitridation） type process was used to grow the gate dielectric film to obtain high channel mobility. The interface properties of 4H-SiC/SiO2 were examined by the measurement of HF l-V, G-V, and C-V over a range of frequencies. The ideal C-V curve with little hysteresis and the frequency dispersion were observed. As a result, the interface state density near the conduction band edge of 4H-SiC was reduced to 2 x 1011 eV-l.cm-2, the breakdown field of the grown oxides was about 9.8 MV/cm, the median peak field- effect mobility is about 32.5 cm2.V-1 .s-1, and the maximum peak field-effect mobility of 38 cm2-V-1 .s-1 was achieved in fabricated lateral 4H-SiC MOSFFETs.

Stacked lateral double-diffused metal–oxide–semiconductor field effect transistor with enhanced depletion effect by surface substrate

A stacked lateral double-diffused metal–oxide–semiconductor field-effect transistor(LDMOS) with enhanced depletion effect by surface substrate is proposed(ST-LDMOS), which is compatible with the traditional CMOS processes. The new stacked structure is characterized by double substrates and surface dielectric trenches(SDT). The drift region is separated by the P-buried layer to form two vertically parallel devices. The doping concentration of the drift region is increased benefiting from the enhanced auxiliary depletion effect of the double substrates, leading to a lower specific on-resistance(Ron,sp). Multiple electric field peaks appear at the corners of the SDT, which improves the lateral electric field distribution and the breakdown voltage(BV). Compared to a conventional LDMOS(C-LDMOS), the BV in the ST-LDMOS increases from 259 V to 459 V, an improvement of 77.22%. The Ron,sp decreases from 39.62 m?·cm^2 to 23.24 m?·cm^2 and the Baliga's figure of merit(FOM) of is 9.07 MW/cm^2.

Influences of fringing capacitance on threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor

Models of threshold voltage and subthreshold swing, including the fringing-capacitance effects between the gate electrode and the surface of the source/drain region, are proposed. The validity of the proposed models is confirmed by the good agreement between the simulated results and the experimental data. Based on the models, some factors impacting the threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor（MOSFET） are discussed in detail and it is found that there is an optimum thickness of gate oxide for definite dielectric constant of gate oxide to obtain the minimum subthreshold swing. As a result, it is shown that the fringing-capacitance effect of a shortchannel GeOI MOSFET cannot be ignored in calculating the threshold voltage and subthreshold swing.

GaSb p-channel metal-oxide-semiconductor field-effect transistor and its temperature dependent characteristics

GaSb p-channel metal-oxide-semiconductor field-effect transistors （MOSFETs） with an atomic layer deposited Al2O3 gate dielectric and a self-aligned Si-implanted source/drain are experimentally demonstrated. Temperature dependent electrical characteristics are investigated. Different electrical behaviors are observed in two temperature regions, and the un- derlying mechanisms are discussed. It is found that the reverse-bias pn junction leakage of the drain/substrate is the main component of the off-state drain leakage current, which is generation-current dominated in the low temperature regions and is diffusion-current dominated in the high temperature regions. Methods to further reduce the off-state drain leakage current are given.

The study on mechanism and model of negative bias temperature instability degradation in P-channel metal-oxide-semiconductor field-effect transistors

Negative Bias Temperature Instability （NBTI） has become one of the most serious reliability problems of metaloxide-semiconductor field-effect transistors （MOSFETs）. The degradation mechanism and model of NBTI are studied in this paper. From the experimental results, the exponential value 0.25-0.5 which represents the relation of NBTI degradation and stress time is obtained. Based on the experimental results and existing model, the reaction-diffusion model with H^＋ related species generated is deduced, and the exponent 0.5 is obtained. The results suggest that there should be H^＋ generated in the NBTI degradation. With the real time method, the degradation with an exponent 0.5 appears clearly in drain current shift during the first seconds of stress and then verifies that H^＋ generated during NBTI stress.

Model and analysis of drain induced barrier lowering effect for 4H-SiC metal semiconductor field effect transistor

Based on an analytical solution of the two-dimensional Poisson equation in the subthreshold region, this paper investigates the behavior of DIBL （drain induced barrier lowering） effect for short channel 4H-SiC metal semiconductor field effect transistors （MESFETs）. An accurate analytical model of threshold voltage shift for the asymmetric short channel 4H-SiC MESFET is presented and thus verified. According to the presented model, it analyses the threshold voltage for short channel device on the L/a （channel length/channel depth） ratio, drain applied voltage VDS and channel doping concentration ND, thus providing a good basis for the design and modelling of short channel 4H-SiC MESFETs device.

Modeling of the drain-induced barrier lowering effect and optimization for a dual-channel 4H silicon carbide metal semiconductor field effect transistor

A new analytical model to describe the drain-induced barrier lowering （DIBL） effect has been obtained by solving the two-dimensional （2D） Poisson＇s equation for the dual-channel 4H-SiC MESFET （DCFET）. Using this analytical model, we calculate the threshold voltage shift and the sub-threshold slope factor of the DCFET, which characterize the DIBL effect. The results show that they are significantly dependent on the drain bias, gate length as well as the thickness and doping concentration of the two channel layers. Based on this analytical model, the structure parameters of the DCFET have been optimized in order to suppress the DIBL effect and improve the performance.

Improved performance of 4H-SiC metal-semiconductor field-effect transistors with step p-buffer layer

An improved 4H-SiC metal-semiconductor field-effect transistors （MESFETs） with step p-buffer layer is proposed, and the static and dynamic electrical performances are analysed in this paper. A step p-buffer layer has been applied not only to increase the channel current, but also to improve the transconductance. This is due to the fact that the variation in p-buffer layer depth leads to the decrease in parasitic series resistance resulting from the change in the active channel thickness and modulation in the electric field distribution inside the channel. Detailed numerical simulations demonstrate that the saturation drain current and the maximum theoretical output power density of the proposed structure are about 30% and 37% larger than those of the conventional structure. The cut-off frequency and the maximum oscillation frequency of the proposed MESFETs are 14.5 and 62 GHz, respectively, which are higher than that of the conventional structure. Therefore, the 4H-SiC MESFETs with step p-buffer layer have superior direct-current and radio-frequency performances compared to the similar devices based on the conventional structure.

Effects of gate-buffer combined with a p-type spacer structure on silicon carbide metal semiconductor field-effect transistors

An improved structure of silicon carbide metal-semiconductor field-effect transistors （MESFET） is proposed for high power microwave applications. Numerical models for the physical and electrical mechanisms of the device are presented, and the static and dynamic electrical performances are analysed. By comparison with the conventional structure, the proposed structure exhibits a superior frequency response while possessing better DC characteristics. A p-type spacer layer, inserted between the oxide and the channel, is shown to suppress the surface trap effect and improve the distribution of the electric field at the gate edge. Meanwhile, a lightly doped n-type buffer layer under the gate reduces depletion in the channel, resulting in an increase in the output current and a reduction in the gate-capacitance. The structural parameter dependences of the device performance are discussed, and an optimized design is obtained. The results show that the maximum saturation current density of 325 mA/mm is yielded, compared with 182 mA/mm for conventional MESFETs under the condition that the breakdown voltage of the proposed MESFET is larger than that of the conventional MESFET, leading to an increase of 79% in the output power density. In addition, improvements of 27% cut-off frequency and 28% maximum oscillation frequency are achieved compared with a conventional MESFET, respectively.

New 4H silicon carbide metal semiconductor field-effect transistor with a buffer layer between the gate and the channel layer

A new 4H silicon carbide metal semiconductor field-effect transistor （4H-SiC MESFET） structure with a buffer layer between the gate and the channel layer is proposed in this paper for high power microwave applications. The physics-based analytical models for calculating the performance of the proposed device are obtained by solving one- and two-dimensional Poisson＇s equations. In the models, we take into account not only two regions under the gate but also a third high field region between the gate and the drain which is usually omitted. The direct-current and the alternating- current performances for the proposed 4H-SiC MESFET with a buffer layer of 0.2 ~tm are calculated. The calculated results are in good agreement with the experimental data. The current is larger than that of the conventional structure. The cutoff frequency （fT） and the maximum oscillation frequency （fmax） are 20.4 GHz and 101.6 GHz, respectively, which are higher than 7.8 GHz and 45.3 GHz of the conventional structure. Therefore, the proposed 4H-SiC MESFET structure has better power and microwave performances than the conventional structure.

Modeling of the drain-induced barrier lowering effect and optimization for a dual-channel 4H silicon carbide metal semiconductor field effect transistor

A new analytical model to describe the drain-induced barrier lowering(DIBL) effect has been obtained by solving the two-dimensional(2D) Poisson’s equation for the dual-channel 4H-SiC MESFET(DCFET).Using this analytical model,we calculate the threshold voltage shift and the sub-threshold slope factor of the DCFET,which characterize the DIBL effect.The results show that they are significantly dependent on the drain bias,gate length as well as the thickness and doping concentration of the two channel layers.Based on this analytical model,the structure parameters of the DCFET have been optimized in order to suppress the DIBL effect and improve the performance.

Progress of power field effect transistor based on ultra-wide bandgap Ga_2O_3 semiconductor material

As a promising ultra-wide bandgap semiconductor, gallium oxide(Ga_2O_3) has attracted increasing attention in recent years. The high theoretical breakdown electrical field(8 MV/cm), ultra-wide bandgap(～ 4.8 eV) and large Baliga's figure of merit(BFOM) of Ga_2O_3 make it a potential candidate material for next generation high-power electronics, including diode and field effect transistor(FET). In this paper, we introduce the basic physical properties of Ga_2O_3 single crystal, and review the recent research process of Ga_2O_3 based field effect transistors. Furthermore, various structures of FETs have been summarized and compared, and the potential of Ga_2O_3 is preliminary revealed. Finally, the prospect of the Ga_2O_3 based FET for power electronics application is analyzed.

Effect of the Si-doped In_(0.49)Ga_(0.51)P barrier layer on the device performance of In_(0.4)Ga_(0.6)As MOSFETs grown on semi-insulating GaAs substrates

In0.4Ga0.6As channel metal-oxide-semiconductor field-effect transistors （MOSFETs） with and without an Si-doped In0.49Ga0.51P barrier layer grown on semi-insulating GaAs substrates have been investigated for the first time. Compared with the In0.4Ga0.6As MOSFETs without an In0.49Ga0.51P barrier layer, In0.4Ga0.6As MOSFETs with an In0.49Ga0.51P barrier layer show higher drive current, higher transconductance, lower gate leakage current, lower subthreshold swing, and higher effective channel mobility. These In0.4Ga0.6As MOSFETs （gate length 2 μm） with an In0.49Ga0.51P barrier layer exhibit a high drive current of 117 mA/mm, a high transconductance of 71.9 mS/mm, and a maximum effective channel mobility of 1266 cm2/（V·s）.

A new physics-based self-heating effect model for 4H-SiC MESFETs

A new self-heating effect model for 4H-SiC MESFETs is proposed based on a combination of an analytical and a computer aided design （CAD） oriented drain current model. The circuit oriented expressions of 4H-SiC low-field electron mobility and incomplete ionization rate, which are related to temperature, are presented in this model, which are used to estimate the self-heating effect of 4H-SiC MESFETs. The verification of the present model is made, and the good agreement between simulated results and measured data of DC I - V curves with the self-heating effect is obtained.

Abnormal oxidation in nickel silicide and nickel germanosilicide in sub-micro CMOS

After post-silicidation annealing at various temperatures for 30 min, abnormal oxidation and agglomeration in nickel silicide and nickel germanosilicide are investigated under different conditions of NiSi, with As-, In-, and Sb-doped Si substrates of nickel germanosilicide without any dopants. The NiSi thickness, dopant species, doping concentration, and silicide process conditions are dominant factors for abnormal oxidation and NiSi agglomeration. Larger dopants than Si, thinner NiSi thickness and SiGe suhstrates, and higher dopant concentrations promote abnormal oxidation and agglomeration.

A two-dimensional threshold voltage analytical model for metal-gate/high-k/SiO_2 /Si stacked MOSFETs

In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor（MOSFET） are investigated.The flat-band voltage is revised by considering the influences of stacked structure and metal-semiconductor work function fluctuation.The two-dimensional Poisson＇s equation of potential distribution is presented.A threshold voltage analytical model for metal-gate/high-k/SiO 2 /Si stacked MOSFETs is developed by solving these Poisson＇s equations using the boundary conditions.The model is verified by a two-dimensional device simulator,which provides the basic design guidance for metal-gate/high-k/SiO 2 /Si stacked MOSFETs.