A binary tree representation is designed in this paper for optimization of wave digital filter（WDF）implementation.To achieve this,an equivalent WDF model of the original circuit is converted into abinary tree repres...A binary tree representation is designed in this paper for optimization of wave digital filter（WDF）implementation.To achieve this,an equivalent WDF model of the original circuit is converted into abinary tree representation at first.This WDF binary tree can then be transformed to several topologies with the same implication,since the WDF adaptors have a symmetrical behavior on their ports.Because the WDF implementation is related to field programmable gate array（FPGA）resource usage and the cycle time of emulation,choosing aproper binary tree topology for WDF implementation can help balance the complexity and performance quality of an emulation system.Both WDF-FPGA emulation and HSpice simulation on the same circuit are tested.There is no significant difference between these two simulations.However,in terms of time consumption,the WDF-FPGA emulation has an advantage over the other.Our experiment also demonstrates that the optimized WDF-FPGA emulation has an acceptable accuracy and feasibility.展开更多
A universal biquadratic filter using single universal voltage conveyor (UVC), two resistors and two capacitors is presented in this paper. The proposed structure has three inputs and one output and can realize all the...A universal biquadratic filter using single universal voltage conveyor (UVC), two resistors and two capacitors is presented in this paper. The proposed structure has three inputs and one output and can realize all the five standard biquadratic filters: low-pass (LP), high-pass (HP), band-pass (BP), band-reject (BR) and all-pass (AP) from the same circuit configuration. The presented universal filter offers low active and passive sensitivities. SPICE (Version 16.5) simulation results using 0.18 μm TSMC technology have been included.展开更多
The widely used sensitive elements of humidity sensors can be divided into 3 types,i.e.,resistor,capacitor,and electrolyte.Humidity sensors consisting of these sensitive elements have corresponding signal processing c...The widely used sensitive elements of humidity sensors can be divided into 3 types,i.e.,resistor,capacitor,and electrolyte.Humidity sensors consisting of these sensitive elements have corresponding signal processing circuit unique to each type of sensitive elements.This paper presents an ispPAC (in-system programmable Programmable Analog Circuit) -based humidity sensor signal processing circuit designed with software method and implemented with in-system programmable simulators.Practical operation shows that humidity sensor signal processing circuits of this kind,exhibit stable and reliable performance.展开更多
This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)tr...This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)transistor level design where MOSFET transistors operating in the saturation region are adopted.The proposed CAB architecture is designed to implement six of thewidely used current mode operations in analog processing systems:addition,subtraction,integration,multiplication,division,and pass operation.The functionality of the proposed CAB is demonstrated through these six operations,where each operation is chosen based on the user’s selection in the CAB interface system.The architecture of the CAB system proposes an optimized way of designing and integrating only three functional cells with the interface circuitry to achieve the six operations.Furthermore,optimized programming and digital tuning circuitry are implemented in the architecture to control and interface with the functional cells.Moreover,these designed programming and tuning circuitries play an essential role in optimizing the performance of the proposed design.Simulation of the proposed CMOS Transistor Based CAB system is carried out using Tanner EDA Tools in 0.35μm standard CMOS technology.The design uses a±1.5 V power supply and results in maximum 3 dB bandwidth of 34.9 MHz and an approximate size of 0.0537 mm2.This demonstrates the advantages of the design over the current state-of-the-art designs presented for comparison in this article.Consequently,the proposed design has a clear aspect of simplicity,low power consumption,and high bandwidth operation,which makes it a suitable candidate for mobile telecommunications applications.展开更多
Previous studies show that interconnects occupy a large portion of the timing budget and area in FPGAs.In this work,we propose a time-multiplexing technique on FPGA interconnects.In order to fully exploit this interco...Previous studies show that interconnects occupy a large portion of the timing budget and area in FPGAs.In this work,we propose a time-multiplexing technique on FPGA interconnects.In order to fully exploit this interconnect architecture,we propose a time-multiplexed routing algorithm that can actively identify qualified nets and schedule them to multiplexable wires.We validate the algorithm by using the router to implement 20 benchmark circuits to time-multiplexed FPGAs.We achieve a 38%smaller minimum channel width and 3.8%smaller circuit critical path delay compared with the state-of-the-art architecture router when a wire can be time-multiplexed six times in a cycle.展开更多
A new universal multiple input multiple output (MIMO) type current-mode biquad employing two dual output current conveyors (DOCCII), one multiple output current controlled current amplifier (MOCCCA) and four passive g...A new universal multiple input multiple output (MIMO) type current-mode biquad employing two dual output current conveyors (DOCCII), one multiple output current controlled current amplifier (MOCCCA) and four passive grounded elements is proposed which can realize all the five basic filtering functions namely, low-pass (LP), high-pass (HP), band-pass (BP), band-stop (BR) and all-pass (AP) in current mode from the same configuration. The centre frequency can be set by the passive elements of the circuit and the quality factor Q0 is electronically tunable through bias currents of the MOCCCA. Therefore, the biquad filter has independent tenability for the and Q0. The active and passive sensitivities of Q0 and are low. The workability of the new configuration has been demonstrated by PSPICE simulation results based upon a CMOS CCII in0.35μm technology.展开更多
基金Supported by the National Natural Science Foundation of China(61271113)
文摘A binary tree representation is designed in this paper for optimization of wave digital filter（WDF）implementation.To achieve this,an equivalent WDF model of the original circuit is converted into abinary tree representation at first.This WDF binary tree can then be transformed to several topologies with the same implication,since the WDF adaptors have a symmetrical behavior on their ports.Because the WDF implementation is related to field programmable gate array（FPGA）resource usage and the cycle time of emulation,choosing aproper binary tree topology for WDF implementation can help balance the complexity and performance quality of an emulation system.Both WDF-FPGA emulation and HSpice simulation on the same circuit are tested.There is no significant difference between these two simulations.However,in terms of time consumption,the WDF-FPGA emulation has an advantage over the other.Our experiment also demonstrates that the optimized WDF-FPGA emulation has an acceptable accuracy and feasibility.
文摘A universal biquadratic filter using single universal voltage conveyor (UVC), two resistors and two capacitors is presented in this paper. The proposed structure has three inputs and one output and can realize all the five standard biquadratic filters: low-pass (LP), high-pass (HP), band-pass (BP), band-reject (BR) and all-pass (AP) from the same circuit configuration. The presented universal filter offers low active and passive sensitivities. SPICE (Version 16.5) simulation results using 0.18 μm TSMC technology have been included.
文摘The widely used sensitive elements of humidity sensors can be divided into 3 types,i.e.,resistor,capacitor,and electrolyte.Humidity sensors consisting of these sensitive elements have corresponding signal processing circuit unique to each type of sensitive elements.This paper presents an ispPAC (in-system programmable Programmable Analog Circuit) -based humidity sensor signal processing circuit designed with software method and implemented with in-system programmable simulators.Practical operation shows that humidity sensor signal processing circuits of this kind,exhibit stable and reliable performance.
基金This work was supported in part by the Geran Galakan Penyelidik Muda Grant(GGPM),Universiti Kebangsaan Malaysia,Selangor,Malaysia under grant GGPM-2021-055.
文摘This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)transistor level design where MOSFET transistors operating in the saturation region are adopted.The proposed CAB architecture is designed to implement six of thewidely used current mode operations in analog processing systems:addition,subtraction,integration,multiplication,division,and pass operation.The functionality of the proposed CAB is demonstrated through these six operations,where each operation is chosen based on the user’s selection in the CAB interface system.The architecture of the CAB system proposes an optimized way of designing and integrating only three functional cells with the interface circuitry to achieve the six operations.Furthermore,optimized programming and digital tuning circuitry are implemented in the architecture to control and interface with the functional cells.Moreover,these designed programming and tuning circuitries play an essential role in optimizing the performance of the proposed design.Simulation of the proposed CMOS Transistor Based CAB system is carried out using Tanner EDA Tools in 0.35μm standard CMOS technology.The design uses a±1.5 V power supply and results in maximum 3 dB bandwidth of 34.9 MHz and an approximate size of 0.0537 mm2.This demonstrates the advantages of the design over the current state-of-the-art designs presented for comparison in this article.Consequently,the proposed design has a clear aspect of simplicity,low power consumption,and high bandwidth operation,which makes it a suitable candidate for mobile telecommunications applications.
文摘Previous studies show that interconnects occupy a large portion of the timing budget and area in FPGAs.In this work,we propose a time-multiplexing technique on FPGA interconnects.In order to fully exploit this interconnect architecture,we propose a time-multiplexed routing algorithm that can actively identify qualified nets and schedule them to multiplexable wires.We validate the algorithm by using the router to implement 20 benchmark circuits to time-multiplexed FPGAs.We achieve a 38%smaller minimum channel width and 3.8%smaller circuit critical path delay compared with the state-of-the-art architecture router when a wire can be time-multiplexed six times in a cycle.
文摘A new universal multiple input multiple output (MIMO) type current-mode biquad employing two dual output current conveyors (DOCCII), one multiple output current controlled current amplifier (MOCCCA) and four passive grounded elements is proposed which can realize all the five basic filtering functions namely, low-pass (LP), high-pass (HP), band-pass (BP), band-stop (BR) and all-pass (AP) in current mode from the same configuration. The centre frequency can be set by the passive elements of the circuit and the quality factor Q0 is electronically tunable through bias currents of the MOCCCA. Therefore, the biquad filter has independent tenability for the and Q0. The active and passive sensitivities of Q0 and are low. The workability of the new configuration has been demonstrated by PSPICE simulation results based upon a CMOS CCII in0.35μm technology.
