Pixelated non-volatile programmable photonic integrated circuits with 20-level intermediate states

Multi-level programmable photonic integrated circuits(PICs)and optical metasurfaces have gained widespread attention in many fields,such as neuromorphic photonics,opticalcommunications,and quantum information.In this paper,we propose pixelated programmable Si_(3)N_(4)PICs with record-high 20-level intermediate states at 785 nm wavelength.Such flexibility in phase or amplitude modulation is achieved by a programmable Sb_(2)S_(3)matrix,the footprint of whose elements can be as small as 1.2μm,limited only by the optical diffraction limit of anin-house developed pulsed laser writing system.We believe our work lays the foundation for laser-writing ultra-high-level(20 levels and even more)programmable photonic systems and metasurfaces based on phase change materials,which could catalyze diverse applications such as programmable neuromorphic photonics,biosensing,optical computing,photonic quantum computing,and reconfigurable metasurfaces.

Design of Gas Sensors Circuits with in-System Programmable Ddevices

In-system programmable devices are products that combined modern electronic techniques and semiconductor techniques.They are indispensable devices in designing modern circuits and systems.This paper presents two practical circuits designed with programmable devices and its design method.By introducing programmable devices into gas sensor circuits,we can further improve system reliability,stability,sensitivity and integration degree,and enhance flexibility of system design.

High-Bandwidth,Low-Power CMOS Transistor Based CAB for Field Programmable Analog Array

This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)transistor level design where MOSFET transistors operating in the saturation region are adopted.The proposed CAB architecture is designed to implement six of thewidely used current mode operations in analog processing systems:addition,subtraction,integration,multiplication,division,and pass operation.The functionality of the proposed CAB is demonstrated through these six operations,where each operation is chosen based on the user’s selection in the CAB interface system.The architecture of the CAB system proposes an optimized way of designing and integrating only three functional cells with the interface circuitry to achieve the six operations.Furthermore,optimized programming and digital tuning circuitry are implemented in the architecture to control and interface with the functional cells.Moreover,these designed programming and tuning circuitries play an essential role in optimizing the performance of the proposed design.Simulation of the proposed CMOS Transistor Based CAB system is carried out using Tanner EDA Tools in 0.35μm standard CMOS technology.The design uses a±1.5 V power supply and results in maximum 3 dB bandwidth of 34.9 MHz and an approximate size of 0.0537 mm2.This demonstrates the advantages of the design over the current state-of-the-art designs presented for comparison in this article.Consequently,the proposed design has a clear aspect of simplicity,low power consumption,and high bandwidth operation,which makes it a suitable candidate for mobile telecommunications applications.

MIXED-GRAINED CMOS FIELD PROGRAMMABLE ANALOG ARRAY FOR SMART SENSORY APPLICATIONS

The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations.

Design of PLC control system of RTG spreader in Qingdao Port Container Terminal

The control method of rubber tyre gantry （RTG） spreader in Qingdao Port Container Terminal is logic board control,which has many shortcomings such as expensive spare parts and high faults.This paper designs a new control system using programmable logic controller （PLC） centralized control to replace the original logic board control.The new system mainly contains complete ELME spreader control scheme design,hardware selection and PLC control program development.Its field application shows that the system has characteristics of high efficiency,low running cost,easy maintenance.

Low-loss chip-scale programmable silicon photonic processor

Chip-scale programmable optical signal processors are often used to flexibly manipulate the optical signals for satisfying the demands in various applications,such as lidar,radar,and artificial intelligence.Silicon photonics has unique advantages of ultra-high integration density as well as CMOS compatibility,and thus makes it possible to develop large-scale programmable optical signal processors.The challenge is the high silicon waveguides propagation losses and the high calibration complexity for all tuning elements due to the random phase errors.In this paper,we propose and demonstrate a programmable silicon photonic processor for the first time by introducing low-loss multimode photonic waveguide spirals and low-random-phase-error Mach-Zehnder switches.The present chip-scale programmable silicon photonic processor comprises a 1×4 variable power splitter based on cascaded Mach-Zehnder couplers(MZCs),four Ge/Si photodetectors,four channels of thermally-tunable optical delaylines.Each channel consists of a continuously-tuning phase shifter based on a waveguide spiral with a micro-heater and a digitally-tuning delayline realized with cascaded waveguide-spiral delaylines and MZSs for 5.68 ps time-delay step.Particularly,these waveguide spirals used here are designed to be as wide as 2μm,enabling an ultralow propagation loss of 0.28 dB/cm.Meanwhile,these MZCs and MZSs are designed with 2-μm-wide arm waveguides,and thus the random phase errors in the MZC/MZS arms are negligible,in which case the calibration for these MZSs/MZCs becomes easy and furthermore the power consumption for compensating the phase errors can be reduced greatly.Finally,this programmable silicon photonic processor is demonstrated successfully to verify a number of distinctively different functionalities,including tunable time-delay,microwave photonic beamforming,arbitrary optical signal filtering,and arbitrary waveform generation.

Design of ispPAC-based Humidity Sensor Signal Processing Circuits

The widely used sensitive elements of humidity sensors can be divided into 3 types,i.e.,resistor,capacitor,and electrolyte.Humidity sensors consisting of these sensitive elements have corresponding signal processing circuit unique to each type of sensitive elements.This paper presents an ispPAC (in-system programmable Programmable Analog Circuit) -based humidity sensor signal processing circuit designed with software method and implemented with in-system programmable simulators.Practical operation shows that humidity sensor signal processing circuits of this kind,exhibit stable and reliable performance.

A NEW APPROACH TO PROGRAMMABLE LOGIC ARRAY FOR SINGLE-CLOCK CMOS

Programmable Logic Array (PLA) is an important building circuit of VLSI chips and some of the FPGA architectures have evolved from the basic PLA architectures. In this letter, a dynamic and static mixed PLA with single-phased clock is presented. Combining both dynamic and static design style rather than introducing additional interface-buffers overcomes the racing problem, thereby saves the chip area. Besides inheriting the advantages of dynamic circuit-low power dissipation and compact structure, this approach also provides high-speed operation.

Precise,programmable biological circuits

Several new components for biological circuits have been developed by researchers,These components are key building blocks for constructing precisely functioning and programmable bio-computers."The ability to combine biological components at will in a modular,plug-and-play fashion means that we now approach the stage when the concept of programming as we know it from software engineering can be applied to

Application of FPGA in Process Tomography Systems

This paper will provide some insights on the application of Field Programmable Gate Array (FPGA) in process tomography. The focus of this paper will be to investigate the performance of the technology with respect to various tomography systems and comparison to other similar technologies including the Application Specific Integrated Circuit (ASIC), Graphics Processing Unit (GPU) and the microcontroller. Fundamentally, the FPGA is primarily used in the Data Acquisition System (DAQ) due to its better performance and better trade-off as compared to competitor technologies. However, the drawback of using FPGA is that it is relatively more expensive.

Design and implementation of high speed TDI CCD timing-driven circuits

The time delay integration charge coupled device(TDI CCD)is the key component in remote sensing systems.The paper analyzes the structure and the working principles of the device according to a customized TDI CCD chip.Employing the special clock resources and large-scale phase locked logic(PLL)in field-programmable gate arrays(FPGA),a timing-driven approach is proposed,using which all timing signals including reset gate,horizontal and vertical timing signals,are implemented in one chip.This not only reduces printed circuit board(PCB)space,but also enhances the portability of the system.By studying and calculating CCD parameters thoroughly,load capacity and power consumption,package,etc,are compared between various candidates chips,and detailed comparison results are also listed in table.Experimental results show that clock generator and driving circuit satisfy the requirements of high speed TDI CCD.

基于FPGA和LabWindows的音频DAC测试方案开发与实现

电子设备集成度的提高对于音频集成电路生产和测试等环节的要求越来越高,尤其是音频数模转换器(Digital to Analog Converter,DAC),本质上为数模混合信号电路,采用数模混合信号自动化测试设备(Automatic Test Equipment,ATE)价格昂贵,而采用传统自动测试仪测试覆盖率低、测试时间长,导致这类电路的测试成本较高且测试产能不足。介绍了一种基于现场可编程门阵列(Field Programmable Gate Array,FPGA)和LabWindows的音频DAC电路测试方案,硬件上用FPGA实现音频测试所需的直接数字频率合成(Direct Digital Frequency Synthesizers,DDFS)模块,软件上通过运用LabWindows自带的采样、加窗、快速傅里叶变换(Fast Fourier Transform,FFT)等数字信号处理函数,快速准确地测试各项模拟参数,并在用户界面(User Interface,UI)显示测试值和后台保存测试数据。

基于CC-Link/LT总线技术的低压供配电监控系统设计

在对低压配电系统研究的基础上,分析了现有系统存在的不足,提出了基于CC-Link/LT总线技术的低压配电监控系统解决方案,实现了对低压供配电设备监视、控制和管理,达到了提高系统可靠性、可控性和快速响应的目的。文中对基于CC-Link/LT总线的低压配电监控系统的硬件组成、网络拓扑进行了较详尽的介绍,并结合实际操作经验,设定了若干系统控制规则,给出了系统各控制部分的程序框图。

全国产化微弱信号调理电路

为更好地处理微弱信号,提出一种新型的多通道信号前端调理模块。该模块不仅具有可编程增益功能,而且还整合了带通滤波器。在保证高输入阻抗和低噪声等关键性能的同时,提出一种全面而创新的调理模块设计方案。该方案的核心是采用可编程增益放大电路,显著提高了模块在放大各类微弱信号时的适应性。此外,利用HC595系列芯片,实现了对增益的精确调控。该放大电路具备26 dB的固定增益和0~84 dB的可调增益范围,工作带宽设定在380~420 kHz。经过系统性能测试,结果表明该调理电路成功满足了设计目标的各项要求。

基于ARM和FPGA的数字多道分析器研制

多道分析器作为γ能谱测量中不可或缺的组件,其性能直接影响能谱仪分辨率及测量精度,传统的多道分析器多采用模拟电路方法或使用数字采集卡实现。模拟多道对于影响能谱仪性能的成形时间、脉冲通过率及死区时间修正等问题上具有一定的局限性,而这会直接影响能谱分析结果;数字采集卡是实现数字采集的计算机扩展卡,成本较高,不利于市场化推广。数字多道分析器对脉冲信号进行全数字采样,将其转化为数字量,利用数字信号处理方法,通过软件实现,完成整个信号分析处理过程,可极大提高系统稳定性与可靠性,相比于前两种方案,优势明显。设计了一款数字多道分析器,采用ARM处理器+高速ADC+FPGA的硬件方案,主要包括AD采样模块、FPGA数据处理模块和以STM32F4为核心的控制和通信模块。使用数字信号处理方法,编写硬件描述代码实现了脉冲信号滤波成型、幅值提取和基线修正等核脉冲处理的关键算法,最后给出探测器核信号经本文设计的数字多道处理后的γ能谱图。根据国内外研究成果及理论基础,经过深入系统理论分析,方法仿真验证,以及实际调试过程,最终研制出一款可商业化实用、完整且高精度的数字多道分析器,并将其应用在低本底γ能谱仪上,其能量分辨率测试均值为6.6791%,能量线性相关度R2在0.9999以上,积分非线性为0.26%。设计的数字化多道分析器采用ARM+FPGA的方式,极大程度降低了系统设计难度和成本,实现了高精度、高速的脉冲信号数字化,测试性能可达到数字采集卡的水平,具有极高的市场应用价值。

一种双三次插值实时超分辨率VLSI设计

视频超分辨率技术具有广阔的应用前景,但基于深度学习方法的算法复杂度过高,难以实现实时计算.因此,近年来研究者们开始探索基于现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)的超分辨率算法加速器,以利用FPGA的优势来提高算法的性能和能耗,实现实时的视频超分辨率.设计了一种基于FPGA的高效高速双三次线性插值超大规模集成电路(Very Large Scale Integration Circuit,VLSI)架构,可用于4倍实时视频超分辨率.该FPGA架构解决了实现双三次插值过程中所需的复杂内存访问模式的问题,并提出了一种基于乒乓操作的数据重排硬件设计,将算法输出的特定顺序数据重新以行为主进行排列,使得硬件能够直接或较为简单地对接HDMI等视频接口.此外,采用状态机、流水线等方式降低设计功耗和减少时序违例,使得整个硬件设计可以更高频率运行.本研究在Zynq-7020 FPGA上实现了硬件架构,能够实时将qHD(960×540)的视频超采样为UHD(3840×2160)高清视频.实验结果表明,该硬件设计只需缓存1行图像像素,延迟仅为9.6μs,帧率达到192.9 Hz,成功实现实时处理.游戏图像数据集的测试结果表明,该设计峰值信噪比最高可达35.67 dB,结构相似度达到96.3%.

一种具有1~128倍可变增益放大器的低功耗Sigma⁃Delta ADC

为满足传感器应用的低功耗需求,设计并实现了一种低功耗Sigma⁃Delta模数转换器(ADC)芯片。该ADC采用一阶全差分开关电容Sigma⁃Delta调制器,且集成了可编程增益放大器(PGA)和Bandgap;使用1.5 bit量化结构,相较于1 bit量化结构减小了3 dB的量化误差;使用优化的反馈电路,减小了电容失配引入的误差;PGA采用轨到轨的运放电路拓扑,增大了整个芯片的电压适应范围。基于180 nm CMOS工艺对该ADC进行了设计和流片。测试结果表明:该Sigma⁃Delta ADC在采样频率512 kHz、过采样率(OSR)为256时,峰值信噪谐波失真比(SNDR)和有效位数(ENOB)分别为75.29 dB和12.21 bit,芯片功耗仅为0.92 mW。芯片能在2.3~5.5 V宽电源电压范围内正常工作,可实现最大128 V/V的增益。适用于小型传感器的信号测量应用,可以满足小型传感器低功耗、高精度的需求。

基于超像素的硅基有机发光二极管微显示器

基于超像素技术,针对彩色硅基OLED(Organic Light Emitting Diode)微显示器,提出一种数字驱动策略,通过复用相邻像素信息,使单像素用于多个相邻像素成像,大幅提高显示分辨率.设计了一种数字驱动彩色OLEDoS(Organic Light Emitting Diode on Silicon)微显示器驱动电路,在120 Hz帧频的条件下,可实现256级灰度和4K显示分辨率,且电路面积和每秒数据传输量仅为传统驱动方式的50%.经测试验证,该驱动电路可实现的OLED像素平均电流范围为13.1 pA~3.74 nA,可满足微显示器近眼显示需求.

基于运放和模拟开关的可编程放大器实验设计

可编程放大器是电子测量常用器件,可扩大输入信号的量程范围。单片可编程放大芯片集成度高、价格不菲,学生对其内部结构了解甚少。实验采用通用运放和模拟开关实现4级量程可编程放大。学生通过实验可更好地理解可编程放大器工作原理,有益于提高学生工程实践创新能力,拓展了实验教学的深度与广度。实验电路成本低、工作稳定,可作为应急方案用于大学生电子设计竞赛等场景。

基于FPGA的室内可见光通信系统设计与实现

可见光通信(Visible Light Communication,VLC)具有通信速率高、绿色环保、安全性高、无需频谱许可等优点,已经成为目前的研究热点。针对可见光通信系统设计复杂及系统通信距离短的问题,文章在接收端加入二级放大电路,进一步改善系统抗干扰能力,同时还研究了室内可见光通信系统的信道模型,并结合高亮发光二极管在室内空间进行了光照强度、接收功率、信噪比及误码率的仿真分析,分析了不同调制方式的抗噪声性能及带宽利用率。将数字信号处理器FPGA(Field Programmable Gate Array,FPGA)作为光通信系统的控制芯片,设计了基于2PPM(Pulse-Phase Modulation,PPM)调制的室内可见光通信系统,通过搭建实验平台验证了该方案下的系统通信性能,在通信距离为3.5m时,误码率小于1×10-5,实验结果表明该通信系统具有误码率低、结构简单等优点,满足高性能室内可见光通信系统的要求。