Temperature-dependent bias-stress-induced electrical instability of amorphous indium-gallium-zinc-oxide thin-film transistors

The time and temperature dependence of threshold voltage shift under positive-bias stress（PBS） and the following recovery process are investigated in amorphous indium-gallium-zinc-oxide（a-IGZO） thin-film transistors. It is found that the time dependence of threshold voltage shift can be well described by a stretched exponential equation in which the time constant τ is found to be temperature dependent. Based on Arrhenius plots, an average effective energy barrier Eτ stress= 0.72 eV for the PBS process and an average effective energy barrier Eτ recovery= 0.58 eV for the recovery process are extracted respectively. A charge trapping/detrapping model is used to explain the threshold voltage shift in both the PBS and the recovery process. The influence of gate bias stress on transistor performance is one of the most critical issues for practical device development.

Contact resistance asymmetry of amorphous indium–gallium–zinc–oxide thin-film transistors by scanning Kelvin probe microscopy

In this work, a method based on scanning Kelvin probe microscopy is proposed to separately extract source/drain（S/D） series resistance in operating amorphous indium–gallium–zinc–oxide（a-IGZO） thin-film transistors. The asymmetry behavior of S/D contact resistance is deduced and the underlying physics is discussed. The present results suggest that the asymmetry of S/D contact resistance is caused by the difference in bias conditions of the Schottky-like junction at the contact interface induced by the parasitic reaction between contact metal and a-IGZO. The overall contact resistance should be determined by both the bulk channel resistance of the contact region and the interface properties of the metalsemiconductor junction.

Double-layer indium doped zinc oxide for silicon thin-film solar cell prepared by ultrasonic spray pyrolysis

Indium doped zinc oxide （ZnO：In） thin films were prepared by ultrasonic spray pyrolysis on corning eagle 2000 glass substrate. 1 and 2 at.% indium doped single-layer ZnO：In thin films with different amounts of acetic acid added in the initial solution were fabricated. The 1 at.% indium doped single-layers have triangle grains. The 2 at.% indium doped single-layer with 0.18 acetic acid adding has the resistivity of 6.82 × 10^-3 Ω. cm and particle grains. The doublelayers structure is designed to fabricate the ZnO：In thin film with low resistivity （2.58 × 10^-3 Ω. cm） and good surface morphology. It is found that the surface morphology of the double-layer ZnO：In film strongly depends on the substratelayer, and the second-layer plays a large part in the resistivity of the doublewlayer ZnO：In thin film. Both total and direct transmittances of the double-layer ZnO：In film are above 80% in the visible light region. Single junction a-Si：H solar cell based on the double-layer ZnO：In as front electrode is also investigated.

Structural,Morphological and Electrical Properties of In-Doped Zinc Oxide Nanostructure Thin Films Grown on p-Type Gallium Nitride by Simultaneous Radio-Frequency Direct-Current Magnetron Co-Sputtering

Zinc oxide （ZnO） is one of the most promising and frequently used semiconductor materials. In-doped nanos- tructure ZnO thin films are grown on p-type gallium nitride substrates by employing the simultaneous rf and dc magnetron co-sputtering technique. The effect of In-doping on structural, morphological and electrical properties is studied. The different dopant concentrations are accomplished by varying the direct current power of the In target while keeping the fixed radio frequency power of the ZnO target through the co-sputtering deposition technique by using argon as the sputtering gas at ambient temperature. The structural analysis confirms that all the grown thin films preferentially orientate along the c-axis with the wurtzite hexagonal crystal structure without having any kind of In oxide phases. The presenting Zn, 0 and In elements＇ chemical compositions are identified with EDX mapping analysis of the deposited thin films and the calculated M ratio has been found to decrease with the increasing In power. The surface topographies of the grown thin films are examined with the atomic force microscope technique. The obtained results reveal that the grown film roughness increases with the In power. The Hall measurements ascertain that all the grown films have n-type conductivity and also the other electrical parameters such as resistivity,mobility and carrier concentration are analyzed.

Low-Frequency Noise in Amorphous Indium Zinc Oxide Thin Film Transistors with Aluminum Oxide Gate Insulator

Low-frequency noise（LFN） in all operation regions of amorphous indium zinc oxide（a-IZO） thin film transistors（TFTs） with an aluminum oxide gate insulator is investigated. Based on the LFN measured results, we extract the distribution of localized states in the band gap and the spatial distribution of border traps in the gate dielectric,and study the dependence of measured noise on the characteristic temperature of localized states for a-IZO TFTs with Al2 O3 gate dielectric. Further study on the LFN measured results shows that the gate voltage dependent noise data closely obey the mobility fluctuation model, and the average Hooge＇s parameter is about 1.18×10^-3.Considering the relationship between the free carrier number and the field effect mobility, we simulate the LFN using the △N-△μ model, and the total trap density near the IZO/oxide interface is about 1.23×10^18 cm^-3eV^-1.

High-throughput fabrication and semi-automated characterization of oxide thin film transistors

High throughput experimental methods are known to accelerate the rate of research,development,and deployment of electronic materials.For example,thin films with lateral gradients in composition,thickness,or other parameters have been used alongside spatially-resolved characterization to assess how various physical factors affect the material properties under varying measurement conditions.Similarly,multi-layer electronic devices that contain such graded thin films as one or more of their layers can also be characterized spatially in order to optimize the performance.In this work,we apply these high throughput experimental methods to thin film transistors(TFTs),demonstrating combinatorial channel layer growth,device fabrication,and semi-automated characterization using sputtered oxide TFTs as a case study.We show that both extrinsic and intrinsic types of device gradients can be generated in a TFT library,such as channel thickness and length,channel cation compositions,and oxygen atmosphere during deposition.We also present a semi-automated method to measure the 44 devices fabricated on a 50 mm×50 mm substrate that can help to identify properly functioning TFTs in the library and finish the measurement in a short time.Finally,we propose a fully automated characterization system for similar TFT libraries,which can be coupled with high throughput data analysis.These results demonstrate that high throughput methods can accelerate the investigation of TFTs and other electronic devices.

Positive gate bias stress-induced hump-effect in elevated-metal metal-oxide thin film transistors

Under the action of a positive gate bias stress, a hump in the subthreshold region of the transfer characteristic is observed for the amorphous indium-gallium-zinc oxide thin film transistor, which adopts an elevated-metal metal-oxide structure. As stress time goes by, both the on-state current and the hump shift towards the negative gate-voltage direction. The humps occur at almost the same current levels for devices with different channel widths, which is attributed to the parasitic transistors located at the channel width edges. Therefore, we propose that the positive charges trapped at the back-channel interface cause the negative shift, and the origin of the hump is considered as being due to more positive charges trapped at the edges along the channel width direction. On the other hand, the hump-effect becomes more significant in a short channel device （L=2 μm）. It is proposed that the diffusion of oxygen vacancies takes place from the high concentration source/drain region to the intrinsic channel region.

IGZO薄膜晶体管生物传感器无标记检测强直性脊柱炎

为了快速检测强直性脊柱炎血清学分子标志物人体白细胞抗原(HLA-B27),开发了一种基于人体白细胞抗原B27(HLA-B27)功能化的氧化铟镓锌(IGZO)薄膜晶体管生物传感器。利用射频磁控溅射技术和微纳加工工艺制备了IGZO薄膜晶体管(IGZO TFT),采用3-氨丙基三乙氧基硅烷(APTES)和抗体对IGZO TFT进行修饰,制备出针对HLA-B27检测的生物传感器。实验结果表明,功能化的IGZO TFT生物传感器具有稳定的电学特性和传感性能。传感器对HLA-B27的检测极限为1 pg/mL,在1 pg/mL至100 ng/mL的范围内均有良好的线性响应。这说明所设计的高性能生物传感器能够有效检测出强直性脊柱炎的标志物。此外,IGZO TFT可以扩展为传感器阵列平台,实现对某种疾病多种标志物的联合检测,在便携式床旁诊断设备的应用中具有巨大潜力。

Influence of white light illumination on the performance of a-IGZO thin film transistor under positive gate-bias stress

The influence of white light illumination on the stability of an amorphous In GaZnO thin film transistor is investigated in this work. Under prolonged positive gate bias stress, the device illuminated by white light exhibits smaller positive threshold voltage shift than the device stressed under dark. There are simultaneous degradations of field-effect mobility for both stressed devices, which follows a similar trend to that of the threshold voltage shift. The reduced threshold voltage shift under illumination is explained by a competition between bias-induced interface carrier trapping effect and photon-induced carrier detrapping effect. It is further found that white light illumination could even excite and release trapped carriers originally exiting at the device interface before positive gate bias stress, so that the threshold voltage could recover to an even lower value than that in an equilibrium state. The effect of photo-excitation of oxygen vacancies within the a-IGZO film is also discussed.

基于原子层沉积IGZO场效应晶体管的接触电阻优化

氧化铟镓锌(IGZO)具有宽带隙、高迁移率、和CMOS后道工艺兼容等优势,可用于下一代高密度三维堆叠存储器。随着IGZO场效应晶体管的尺寸不断微缩,源漏接触电阻在开态时会主导器件总电阻。因此,IGZO场效应晶体管的接触电阻优化成为需要研究的一个关键问题。本文采用原子层沉积的IGZO作为沟道并制备出场效应晶体管,探究了接触金属种类及后退火工艺对IGZO场效应晶体管接触电阻的影响。结果表明,退火前镍和钛的接触电阻相当。但在Ar/O2氛围、250℃条件下退火2小时后,采用钛接触的IGZO场效应晶体管的接触电阻降低到镍接触的8.3%,实现接触电阻低至0.86 kΩ·μm,同时阈值电压正移实现了增强型器件。与此同时,制备出超短沟长(Lch=80 nm)的IGZO场效应晶体管,开态电流高达412.2μA/μm、亚阈值摆幅为88.6 mV/dec,漏致势垒降低系数低至0.02 V/V。这些结果表明,通过优化接触金属种类及后退火条件,可实现高性能IGZO场效应晶体管,并为IGZO大规模实际应用提供新思路。

Microstructure and optoelectronic properties of galliumtitanium-zinc oxide thin films deposited by magnetron sputtering

Gallium-titanium-zinc oxide(GTZO) transparent conducting oxide(TCO) thin films were deposited on glass substrates by radio frequency magnetron sputtering. The dependences of the microstructure and optoelectronic properties of GTZO thin films on Ar gas pressure were observed. The X-ray diffraction(XRD) and scanning electron microscopy(SEM) results show that all the deposited films are polycrystalline with a hexagonal structure and have a preferred orientation along the c-axis perpendicular to the substrate. With the increment of Ar gas pressure, the microstructure and optoelectronic properties of GTZO thin films will be changed. When Ar gas pressure is 0.4 Pa, the deposited films possess the best crystal quality and optoelectronic properties.

Threshold voltage tuning and printed complementary transistors and inverters based on thin films of carbon nanotubes and indium zinc oxide

Carbon nanotubes （CNTs） have emerged as an important material for printed macroelectronics. However, achieving printed complementary macroelectronics solely based on CNTs is difficult because it is still challenging to make reliable n-type CNT transistors. In this study, we report threshold voltage （Vth） tuning and printing of complementary transistors and inverters composed of thin films of CNTs and indium zinc oxide （IZO） as p-type and n-type transistors, respectively. We have optimized the Vth of p-type transistors by comparing Ti/Au and Ti/Pd as source/drain electrodes, and observed that CNT transistors with Ti/Au electrodes exhibited enhancement mode operation （Vth 〈 0）. In addition, the optimized In：Zn ratio offers good n-type transistors with high on-state current （Ion） and enhancement mode operation （Vth 〉 0）. For example, an In：Zn ratio of 2：1 yielded an enhancement mode n-type transistor with Vth - 1 V and Ion of 5.2 μA. Furthermore, by printing a CNT thin film and an IZO thin film on the same substrate, we have fabricated a complementary inverter with an output swing of 99.6% of the supply voltage and a voltage gain of 16.9. This work shows the promise of the hybrid integration of p-type CNT and n-type IZO for complementary transistors and circuits.

氧分压对磁控溅射制备IGZO薄膜光电特性的影响

通过磁控溅射技术在玻璃基板上制备氧化铟镓锌（IGZO）薄膜，为了研究不同氧分压对IGZO薄膜结构及光电特性的影响，在不同的氧分压0，0．015，0．06和0．24Pa下制备了不同样品。样品的沉积速率、成分结构、面电阻及光电性质分别用椭偏仪、X射线光电子能谱（XPS）和四点探针等方法进行了测量。实验结果表明，随着氧分压的增大，IGZO薄膜的沉积速率呈下降趋势，不同氧分压的IGZO薄膜的元素比例（In：Ga：Zn）差异不大，在可见光的范围内其氧分压为0Pa以上时，IGZO薄膜平均透过率均超过80％，阻值随氧分压的增加而增大。制作了不同氧分压以IGZO为沟道层的薄膜晶体管，其迁移率为5．93～9．42cm^2·V^-1·s^-1，阈值电压为3．8～9．2V。

基于喷墨打印的In_2O_3/IGZO TFT的电学性能

利用喷墨打印技术制备了非晶铟镓锌氧化物(IGZO)薄膜、铟氧化物(In_2O_3)薄膜和性能明显改善的双层In_2O_3/IGZO异质结沟道薄膜,研究了薄膜的物理与电学特性。结果表明,喷墨打印制备的金属氧化物薄膜具有较高的光学透过率与较低的表面粗糙度;嵌入的In_2O_3层薄膜能减小IGZO与In_2O_3间的界面缺陷,明显提高In_2O_3/IGZO薄膜晶体管(TFT)的性能及其偏压稳定性。随着IGZO中In含量的增加,载流子浓度升高,器件的迁移率增大,但In_2O_3与IGZO间能级势垒会逐渐降低,最后导致难以控制关态电流和阈值电压,因此,适当调整In的比例有利于获得较高器件性能的In_2O_3/IGZO异质结沟道TFT。

钝化层对背沟道刻蚀型IGZO薄膜晶体管的影响

本文制备了氧化硅、聚酰亚胺以及氧化硅-聚酰亚胺堆叠结构钝化层的非晶铟镓锌氧背沟道刻蚀型薄膜晶体管.与传统氧化硅钝化层薄膜晶体管相比,聚酰亚胺钝化层薄膜晶体管的电学特性大幅提高,场效应迁移率从4.7提升至22.4 cm^(2)/(V·s),亚阈值摆幅从1.6降低至0.28 V/decade,电流开关比从1.1×10^(7)提升至1.5×10^(10),负偏压光照稳定性下的阈值电压偏移从–4.8 V下降至–0.7 V.电学特性的改善可能是由于氢向聚酰亚胺钝化层扩散减少了背沟道的浅能级缺陷.

PVD工艺对IGZO薄膜结晶化的影响

在G4.5实验线上,采用射频磁控溅射法,通过优化成膜时的温度、功率、气体流量比、退火温度和膜层厚度等参数,以XRD,HR-TEM,NBED和EDS进行表征,研究制备结晶IGZO的工艺参数及其对薄膜晶体管(TFT)电性的影响。结果表明,当IGZO膜层厚度达到3000A以上时结晶效果明显,且不受其他因素影响;成膜功率对IGZO结晶现象有加强作用,功率越高越易结晶;成膜温度和氧气/氩气(O2/Ar)气体比例对IGZO结晶影响不大;成膜完成后经过600℃的退火处理可有效地促进IGZO的再结晶。通过优化IGZO成膜条件,制备出迁移率达29.6 cm^2/(V·s)的背沟道刻蚀结构IGZO TFT,比非晶IGZO TFT提高约3倍,显著地改善了IGZO TFT的电学特性。

金属氧化物（IGZO）TFT-LCD的工艺技术发展趋势及方向

铟镓锌氧化物IGZO（indiumgalliumzincoxide）是用于新一代薄膜液晶显示屏薄膜晶体管沟道层的材料。研究铟镓锌金属氧化物IGZO在TFT—LCD制造应用中的工艺技术发展趋势及方向。分析了铟镓锌氧化物IGZO在TFT—LCD中的作用和使用现状，分析了TFT—LCD液晶显示器的功能特性和技术特点。结合金属氧化物IGZO的应用，阐述了未来TFT—LCD液晶显示器发展的趋势和方向，TFT—LCD的工艺技术将向着高集成度，高环保性、高分辨率、高水平垂直角、高显示亮度、长使用寿命周期等方向发展，随着大面积低温多晶硅TFT—LCD的使用，TFT—LCD发展空间广阔，将迅速成为当前和未来液晶显示器的主流产品。

Degradation of current–voltage and low frequency noise characteristics under negative bias illumination stress in InZnO thin film transistors

The instabilities of indium–zinc oxide thin film transistors under bias and/or illumination stress are studied in this paper. Firstly, illumination experiments are performed, which indicates the variations of current–voltage characteristics and electrical parameters（such as threshold voltage and sub-threshold swing） are dominated by the stress-induced ionized oxygen vacancies and acceptor-like states. The dependence of degradation on light wavelength is also investigated. More negative shift of threshold voltage and greater sub-threshold swing are observed with the decrease of light wavelength.Subsequently, a negative bias illumination stress experiment is carried out. The degradation of the device is aggravated due to the decrease of recombination effects between ionized oxygen vacancies and free carriers. Moreover, the contributions of ionized oxygen vacancies and acceptor-like states are separated by using the mid-gap method. In addition, ionized oxygen vacancies are partially recombined at room temperature and fully recombined at high temperature. Finally, low-frequency noise is measured before and after negative bias illumination stress. Experimental results show few variations of the oxide trapped charges are generated during stress, which is consistent with the proposed mechanism.

沟道层带尾态密度和厚度对a-IGZO薄膜晶体管特性影响的数值仿真

建立了非晶铟镓锌氧化物(a-IGZO)薄膜晶体管(thin-film transistor,简称TFT)的仿真模型,仿真分析了IGZO半导体层带尾态密度和沟道层厚度两个参数对IGZO TFTs特性的影响规律.研究结果表明,当半导体层带尾态密度增加到1.5×10^(19)cm^(-3)·eV^(-1)及以上时,器件电学特性受深陷阱态影响劣化,亚阈值摆幅增加;沟道层薄膜厚度较小(<40 nm)时,器件的转移特性良好,当沟道层薄膜厚度超过40 nm时,器件的电学特性劣化,关态电流增加,开关比降低,亚阈值摆幅增加.本工作数值仿真分析方法可为设计制备IGZO TFTs提供一定的理论基础和实验指导.

Pd/PdO_(x)/IGZO肖特基二极管及其全波整流电路的研究

铟镓锌氧化物(IGZO)是一种极具应用发展前景且已在显示领域有一定市场规模的氧化物半导体材料。目前其研究主要集中在薄膜晶体管上,而关于由其制备的薄膜二极管及其相关电路的研究较少。本工作通过沉积氧化钯(PdO_(x))作为肖特基电极接触形成界面富氧状态,实现了低氧空位界面缺陷态密度的高质量肖特基接触,制备了高性能IGZO肖特基势垒二极管(SBD),实现了接近理想值的理想因子1.09、高达3.3×10^(6)的电流开关比以及0.80 eV的肖特基势垒高度。基于该SBD进而制备了桥式整流电路,实现了正弦波的全波整流,且在500 Hz低频下输出电压幅值损耗小于1 V。