SiC gate-controlled bipolar field effect composite transistor with polysilicon region for improving on-state current

A novel silicon carbide gate-controlled bipolar field effect composite transistor with poly silicon region(SiC GCBTP)is proposed.Different from the traditional electrode connection mode of SiC vertical diffused MOS(VDMOS),the P+region of P-well is connected with the gate in SiC GCBTP,and the polysilicon region is added between the P+region and the gate.By this method,additional minority carriers can be injected into the drift region at on-state,and the distribution of minority carriers in the drift region will be optimized,so the on-state current is increased.In terms of static characteristics,it has the same high breakdown voltage(811 V)as SiC VDMOS whose length of drift is 5.5μm.The on-state current of SiC GCBTP is 2.47×10^(-3)A/μm(V_(G)=10 V,V_(D)=10 V)which is 5.7 times of that of SiC IGBT and 36.4 times of that of SiC VDMOS.In terms of dynamic characteristics,the turn-on time of SiC GCBTP is only 0.425 ns.And the turn-off time of SiC GCBTP is similar to that of SIC insulated gate bipolar transistor(IGBT),which is 114.72 ns.

Novel lateral insulated gate bipolar transistor on SOI substrate for optimizing hot-carrier degradation

A novel lateral insulated gate bipolar transistor on a silicon-on-insulator substrate SOI-LIGBT with a special low-doped P-well structure is proposed.The P-well structure is added to attach the P-body under the channel so as to reduce the linear anode current degradation without additional process.The influence of the length and depth of the P-well on the hot-carrier HC reliability of the SOI-LIGBT is studied.With the increase in the length of the P-well the perpendicular electric field peak and the impact ionization peak diminish resulting in the reduction of the hot-carrier degradation. In addition the impact ionization will be weakened with the increase in the depth of the P-well which also makes the hot-carrier degradation decrease.Considering the effect of the low-doped P-well and the process windows the length and depth of the P-well are both chosen as 2 μm.

A dual-gate and dielectric-inserted lateral trench insulated gate bipolar transistor on a silicon-on-insulator substrate

In this paper, a novel dual-gate and dielectric-inserted lateral trench insulated gate bipolar transistor （DGDI LTIGBT） structure, which features a double extended trench gate and a dielectric inserted in the drift region, is proposed and discussed. The device can not only decrease the specific on-resistance Ron,sp , but also simultaneously improve the temperature performance. Simulation results show that the proposed LTIGBT achieves an ultra-low on-state voltage drop of 1.31 V at 700 A·cm-2 with a small half-cell pitch of 10.5 μm, a specific on-resistance R on,sp of 187 mΩ·mm2, and a high breakdown voltage of 250 V. The on-state voltage drop of the DGDI LTIGBT is 18% less than that of the DI LTIGBT and 30.3% less than that of the conventional LTIGBT. The proposed LTIGBT exhibits a good positive temperature coefficient for safety paralleling to handling larger currents and enhances the short-circuit capability while maintaining a low self-heating effect. Furthermore, it also shows a better tradeoff between the specific on-resistance and the turnoff loss, although it has a longer turnoff delay time.

Insulated gate bipolar transistor inverter for arc welding

This paper introduces the Insulated gate bipolar transistor(IGBT)in- verter for arc welding.The principle of the inverter,the structure and charac- teristics of IGBT and the current feedback system using LEM current transduc- er are discussed.By the measurement of its efficiency and power factor and the tests of welding processes,the developed 150A IGBT inverter proves to be a kind of energy-saving portable power supply for arc welding with broad prospects.

A high voltage silicon-on-insulator lateral insulated gate bipolar transistor with a reduced cell-pitch

A high voltage（〉 600 V） integrable silicon-on-insulator（SOI） trench-type lateral insulated gate bipolar transistor（LIGBT） with a reduced cell-pitch is proposed.The LIGBT features multiple trenches（MTs）：two oxide trenches in the drift region and a trench gate extended to the buried oxide（BOX）.Firstly,the oxide trenches enhance electric field strength because of the lower permittivity of oxide than that of Si.Secondly,oxide trenches bring in multi-directional depletion,leading to a reshaped electric field distribution and an enhanced reduced-surface electric-field（RESURF） effect.Both increase the breakdown voltage（BV）.Thirdly,oxide trenches fold the drift region around the oxide trenches,leading to a reduced cell-pitch.Finally,the oxide trenches enhance the conductivity modulation,resulting in a high electron/hole concentration in the drift region as well as a low forward voltage drop（Von）.The oxide trenches cause a low anode-cathode capacitance,which increases the switching speed and reduces the turn-off energy loss（Eoff）.The MT SOI LIGBT exhibits a BV of 603 V at a small cell-pitch of 24 μm,a Von of 1.03 V at 100 A/cm-2,a turn-off time of 250 ns and Eoff of 4.1×10？3 mJ.The trench gate extended to BOX synchronously acts as dielectric isolation between high voltage LIGBT and low voltage circuits,simplifying the fabrication processes.

基于注意力机制的CNN-BiLSTM的IGBT剩余使用寿命预测

针对绝缘栅双极型晶体管(IGBT)可靠性问题,提出了一种融合卷积神经网络(CNN)、双向长短期记忆(BiLSTM)网络和注意力机制的剩余使用寿命(RUL)预测模型,可用于IGBT的寿命预测。模型中使用CNN提取特征参数,BiLSTM提取时序信息,注意力机制加权处理特征参数。使用IGBT加速老化数据集对提出的模型进行验证。结果表明,对比自回归差分移动平均(ARIMA)、长短期记忆(LSTM)、多层LSTM(Multi-LSTM)、 BiLSTM预测模型,在均方根误差和决定系数等评价指标方面该模型的性能最优。验证了提出的寿命预测模型对IGBT失效预测是有效的。

基于焊层裂纹扩展的IGBT性能退化建模与分析

在疲劳载荷作用下,绝缘栅双极型晶体管(insulated gate bipolar transistor,IGBT)会发生结构损伤与性能退化,影响电力电子系统可靠性。对此,首先基于传热学理论推导焊层疲劳裂纹长度与热阻的关系,并以Darveaux模型表征IGBT焊层裂纹演化规律,提出一种IGBT性能退化模型及其待定系数的估计方法。其次,考虑实际工况的非平稳特征,利用响应面法建立IGBT变幅疲劳载荷模型,并基于雨流计数法与线性累积损伤准则实现IGBT性能退化量的评估。最后,以一款IGBT产品为例,实施功率循环试验,基于试验数据开展性能退化建模与分析,验证了模型与算法的有效性。

基于Bo-BiLSTM网络的IGBT老化失效预测方法

针对绝缘栅双极型晶体管(IGBT)受热应力冲击后对其进行老化失效预测精度不高的情况,提出一种基于贝叶斯优化(Bo)-双向长短期记忆(BiLSTM)网络的IGBT老化失效预测方法。首先分析IGBT模块老化失效原理,然后基于NASA老化实验数据集建立失效特征数据库,最后利用Matlab软件构造Bo-BiLSTM网络预测失效特征参数数据。选取常用回归预测性能评估指标将长短期记忆(LSTM)网络模型、BiLSTM网络模型与Bo-BiLSTM网络模型的预测结果进行对比分析。结果表明,Bo-BiLSTM网络的模型拟合精度更高,基于Bo-BiLSTM网络的IGBT老化失效预测方法具有较好的预测效果,能够应用于IGBT的失效预测。

IGBT并联应用均流控制技术综述

绝缘栅双极型晶体管IGBT(insulated-gate bipolar transistor)在现代电力电子技术中应用广泛,在某些单个器件性能达不到设计要求的工作场合,IGBT的并联使用成为一种经济可行的方法。多模块IGBT并联应用可以简化电路结构,增大变流器输出功率,提高装置功率密度。IGBT并联应用过程中,器件本体的动、静态特性及结温的差异,驱动电路结构及功率回路不对称性,伴随IGBT长期使用出现的老化或失效等问题,都会引起并联IGBT支路电流的不均衡,影响系统的可靠性和稳定性。对国内外IGBT并联应用所关注的研究热点进行了调研分析,总结了IGBT并联动、静态电流不均衡产生的原理及影响,分析了电流均衡控制原理的差异。从功率回路均流控制和驱动回路均流控制两个方面,对IGBT并联应用均流控制的工作特性进行了分析总结和技术对比,并对IGBT并联均流技术的发展方向进行了展望。

基于导通压降的大容量IGBT模块结温观测与误差分析研究

压接式绝缘栅双极性晶体管PP-IGBT(press-pack insulated gate bipolar transistor)模块因其优越的电气性能和可靠性,广泛应用于柔性直流换流阀等大功率应用场景。IGBT芯片结温的准确观测对于其运行状态的监测与剩余寿命的评估都非常重要。已有结温观测方法多是针对键合引线式IGBT,未考虑到压接式模块的特性,无法直接应用。首先,针对大容量换流阀中的压接式IGBT,提出了一种实用的模块导通压降与结温标定方法,并对结温在线估计的误差进行了全面分析。然后,基于ABB公司5SNA 3000K452300压接式IGBT模块(4500 V,3000 A)设计了结温标定方案,包括实验电路、温度标定范围选择、结温控制方式、测量电路及标定实验步骤。最后,基于脉冲测试平台,对所提方法进行了验证。实验结果表明,所提结温标定与观测方案有效,结温观测误差在±5℃以内,且能适用压接式IGBT模块存在差异的情况。

计及电热参数更新的高速列车牵引整流器IGBT模块寿命评估

绝缘栅双极晶体管(IGBT)作为列车变流器的关键部件,其寿命受老化过程中参数变化的影响,为此提出了一种计及电热参数更新的IGBT模块寿命预测方法。首先,利用实车采集到的外部电压、电流数据结合变流器调制策略推导IGBT的驱动信号,进而获得单个IGBT的电压电流;其次,基于数据手册建立Foster热网络模型获取IGBT的结温;之后考虑到实际中IGBT的老化过程,提出一种IGBT结温计算过程中热阻和导通压降的更新策略;最后通过寿命模型对IGBT进行损伤度估算,并通过蒙特卡洛(Monte-Carlo)模拟评估器件寿命计算过程中的不确定性,取得可靠性变化曲线。

一种基于开通栅极电压的新型IGBT键合线老化监测方法

绝缘栅双极型晶体管(insulated gate bipolar transistors,IGBT)的可靠运行是牵引变流器安全和性能的重要保障。键合线老化作为IGBT的一种常见失效模式,对其进行监测具有重要意义。文中提出一种基于开通栅极电压ugem的键合线老化监测方法,该方法可有效避免温度和负载电流带来的影响。首先,基于IGBT等效电路模型,系统分析ugem受键合线断裂影响的原因;其次,利用双脉冲测试进行验证,同时对温度和负载电流带来的影响进行分析;在此基础上,考虑到使用ugem局部特征将受到温度和电流的干扰,提出将开通栅极电压整体波形用于键合线老化的监测,并进一步利用有监督的线性判别分析进行数据降维以及采用支持向量机实现键合线断裂根数的检测。最后,通过实验对所提监测方法的有效性进行验证。

感应加热电源的IGBT驱动保护系统设计

为提高感应加热电源的绝缘栅双极型晶体管(IGBT)信号源与保护电路的稳定性,设计了应用于工业化低频大功率感应加热电源设备的IGBT驱动保护系统。系统整体采用复杂可编程逻辑器件(CPLD)+数字信号处理(DSP)协同工作方案,由低频正弦脉冲宽度调制(SPWM)技术控制,以脉冲变压器2ED300C17-S为IGBT保护电路的核心,设计了IGBT故障处理电路、退饱和检测电路与有源钳位电路等多种保护电路。对系统进行理论分析与Matlab/Simulink仿真,搭建了实物测试平台。试验结果表明,当工件加热到900℃时,逆变器输出功率参数与负载端功率参数达到大功率感应加热电源要求,且信号源输出稳定性高、保护电路响应时间快。该设计为相关工业化应用提供技术支持。

基于LSTM网络的IGBT寿命预测方法研究

针对IGBT工作时承受热应力与电应力循环冲击导致疲劳失效的问题,提出一种基于长短期记忆(LSTM)网络的寿命预测方法。利用NASA预测中心提供的加速老化数据集,分析并选取集电极-发射极的瞬态尖峰电压作为失效特征参数,通过Matlab构建LSTM网络,采用Adam优化算法来训练网络,实现对失效特征参数数据的预测,并选取三项性能评估指标与ARIMA模型及ELMAN神经网络模型的预测进行对比分析。结果显示,LSTM网络模型预测的均方根误差为0.0476,平均绝对误差为0.0322,平均绝对百分误差为0.4917%,LSTM网络模型的预测精度更高,能够更好地实现IGBT的寿命预测,也对其他电力电子器件的寿命预测有一定的参考价值。

650 V IGBT横向变掺杂终端的设计与优化

绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor,IGBT)器件的最重要参数之一是击穿电压(Breakdown Voltage,BV),影响IGBT器件BV的因素包括:平面工艺PN结扩散终端、界面电荷、杂质在Si、SiO2中具有不同分凝系数等。其中影响IGBT器件耐压能力的重要因素是芯片终端结构的设计,终端区耗尽层边界的曲率半径制约了BV的提升,为了能够减少曲率效应和增大BV,可以采取边缘终端技术。通过Sentaurus TCAD计算机仿真软件,采取横向变掺杂(Variable Lateral Doping,VLD)技术,设计了一款650 V IGBT功率器件终端,在VLD区域利用掩膜技术刻蚀掉一定的硅,形成浅凹陷结构。仿真结果表明,这一结构实现了897 V的耐压,终端长度为256μm,与同等耐压水平的场限环终端结构相比,终端长度减小了19.42%,且最大表面电场强度为1.73×10^(5)V/cm,小于硅的临界击穿电场强度(2.5×10^(5)V/cm);能在极大降低芯片面积的同时提高BV,并且提升了器件主结的耐压能力。此外,工艺步骤无增加,与传统器件制造工艺相兼容。

高压大功率IGBT器件绝缘结构的电场计算研究综述

随着高压直流输电技术的发展,高压大功率绝缘栅双极型晶体管(insulated gate bipolar transistor,IGBT)器件被广泛应用于各类高压大容量电力换流和控制装备中。然而,在高压大功率IGBT器件的研制过程以及工程应用中,器件内部局部放电现象乃至击穿现象频繁发生,给器件绝缘设计带来巨大挑战。要想实现良好器件绝缘设计,就需要获得器件内部的电场分布,因此实现器件内部电场的准确计算至关重要。文中全面回顾器件内部绝缘结构的建模和计算方法的发展历程,从封装绝缘电场计算、芯片绝缘电场计算以及芯片和封装绝缘耦合电场计算3个方面介绍相关研究的发展历程、适用范围以及相应的不足,最后展望未来器件内绝缘结构电场计算的发展方向。

压接型IGBT器件短路失效管壳爆炸特性及防护方法

压接型绝缘栅双极性晶体管(insulated gate bipolar transistor,IGBT)作为现有柔性直流输电设备的核心部件,在实际应用中,由于承受高电压、大电流的工作环境,容易发生短路过流失效,进而造成的结构爆炸现象。为研究这一爆炸现象的破坏效应及其防护,该文结合多组模拟模块化多电平工况实验,得到IGBT器件短路过流失效爆炸后外壳结构的变形特征。结合电气能量特性的分析和实际爆炸失效形貌特点,建立该IGBT器件结构的数值仿真模型,初步确定实际爆炸过程中的等效TNT爆炸当量。在此基础上,从提高结构自身抗爆能力、增加能量外泄通道、替换结构材料等角度开展IGBT器件的结构优化设计,并进行相关试验验证。结果表明,将管壳的陶瓷材料替换为纤维增强复合材料可有效提高结构的防爆性能,降低器件的破坏程度。

Improving dynamic characteristics for IGBTs by using interleaved trench gate

A novel trench insulated gate bipolar transistor(IGBT) with improved dynamic characteristics is proposed and investigated. The poly gate and poly emitter of the proposed IGBT are arranged alternately along the trench. A self-biased p-MOSFET is formed on the emitter side. Owing to this unique three-dimensional(3D) trench architecture, both the turnoff characteristic and the turn-on characteristic can be greatly improved. At the turn-off moment, the maximum electric field and impact ionization rate of the proposed IGBT decrease and the dynamic avalanche(DA) is suppressed. Comparing with the carrier-stored trench gate bipolar transistor(CSTBT), the turn-off loss(E_(off)) of the proposed IGBT also decreases by 31% at the same ON-state voltage. At the turn-on moment, the built-in p-MOSFET reduces the reverse displacement current(I_(G_dis)), which is conducive to lowing dI_(C)/d_(t). As a result, compared with the CSTBT with the same turn-on loss(E_(on)), at I_(C) = 20 A/cm^(2), the proposed IGBT decreases by 35% of collector surge current(I_(surge)) and 52% of dI_(C)/d_(t).

散热底板对IGBT模块功率循环老化寿命的影响

功率半导体模块通常采用减小结壳热阻的方式来降低工作结温,集成Pin-Fin基板代替平板基板是一种有效的选择。两种封装结构的热阻抗特性不同,可能对其失效机理及应用寿命产生影响。针对平板基板和集成Pin-Fin基板两种常见车规级IGBT模块进行了相同热力测试条件(结温差100 K,最高结温150℃)下的功率循环试验,结果表明,散热更强的Pin-Fin模块功率循环寿命低于平板模块。失效分析显示,两者失效模式均为键合线脱附,但Pin-Fin模块的键合失效点集中在芯片中心区域,而平板模块的键合失效点则较为分散。基于电-热-力耦合分析方法,建立功率循环试验的有限元仿真模型,结果表明,Pin-Fin模块的芯片温变梯度更大,芯片中心区域键合点温度更高,使芯片中心区域的键合点塑性变形更大,导致其寿命较平板模块更短,与试验结果吻合。

IGBT器件级物理模型的FPGA设计与实现及在环验证

基于硬件在环(HIL)仿真,研究了绝缘栅双极型晶体管(IGBT)器件级Hefner物理模型及其求解算法与优化方法,在现场可编程门阵列(FPGA)上设计并实现了Hefner优化模型,并基于PYNQ框架对其进行了在环验证。首先,分析并仿真了Hefner物理模型与其求解算法,提出并训练了一个前馈神经网络用以拟合模型中的一组非线性函数;接着,在FPGA上设计并验证了Hefner优化模型IP核,并使用基于PYNQ框架的FPGA在环验证方法对其进行了板级验证;最后,用IKW50N60H3和FGA25N120两种型号的IGBT器件对IP核进行了实例验证。结果表明,Hefner优化模型能准确地反映IGBT的开关瞬态特性;在Zynq 7020芯片的处理器系统(PS)端运行PYNQ框架,可编程逻辑(PL)端时钟频率为100 MHz时,实现60 000个时间步长的时间为212 s,是软件运行同样次数所用时间(341 s)的62%,FPGA加速明显。