Novel lateral insulated gate bipolar transistor on SOI substrate for optimizing hot-carrier degradation

A novel lateral insulated gate bipolar transistor on a silicon-on-insulator substrate SOI-LIGBT with a special low-doped P-well structure is proposed.The P-well structure is added to attach the P-body under the channel so as to reduce the linear anode current degradation without additional process.The influence of the length and depth of the P-well on the hot-carrier HC reliability of the SOI-LIGBT is studied.With the increase in the length of the P-well the perpendicular electric field peak and the impact ionization peak diminish resulting in the reduction of the hot-carrier degradation. In addition the impact ionization will be weakened with the increase in the depth of the P-well which also makes the hot-carrier degradation decrease.Considering the effect of the low-doped P-well and the process windows the length and depth of the P-well are both chosen as 2 μm.

A dual-gate and dielectric-inserted lateral trench insulated gate bipolar transistor on a silicon-on-insulator substrate

In this paper, a novel dual-gate and dielectric-inserted lateral trench insulated gate bipolar transistor （DGDI LTIGBT） structure, which features a double extended trench gate and a dielectric inserted in the drift region, is proposed and discussed. The device can not only decrease the specific on-resistance Ron,sp , but also simultaneously improve the temperature performance. Simulation results show that the proposed LTIGBT achieves an ultra-low on-state voltage drop of 1.31 V at 700 A·cm-2 with a small half-cell pitch of 10.5 μm, a specific on-resistance R on,sp of 187 mΩ·mm2, and a high breakdown voltage of 250 V. The on-state voltage drop of the DGDI LTIGBT is 18% less than that of the DI LTIGBT and 30.3% less than that of the conventional LTIGBT. The proposed LTIGBT exhibits a good positive temperature coefficient for safety paralleling to handling larger currents and enhances the short-circuit capability while maintaining a low self-heating effect. Furthermore, it also shows a better tradeoff between the specific on-resistance and the turnoff loss, although it has a longer turnoff delay time.

Insulated gate bipolar transistor inverter for arc welding

This paper introduces the Insulated gate bipolar transistor(IGBT)in- verter for arc welding.The principle of the inverter,the structure and charac- teristics of IGBT and the current feedback system using LEM current transduc- er are discussed.By the measurement of its efficiency and power factor and the tests of welding processes,the developed 150A IGBT inverter proves to be a kind of energy-saving portable power supply for arc welding with broad prospects.

Positive Bias Temperature Instability and Hot Carrier Injection of Back Gate Ultra-thin-body In0.53Ga0.47As-on-Insulator n-Channel Metal-Oxide-Semiconductor Field-Effect Transistor

Ultra-thin-body （UTB） In0.53Ga0.47As-on-insulator （In0.53Ga0.47As-OI） structures with thicknesses of 8 and 15nm are realized by transferring epitaxially grown In0.53Ga0.47As layers to silicon substrates with 15-nmthick A12 03 as a buried oxide by using the direct wafer bonding method. Back gate n-channel metal-oxidesemiconductor field-effect transistors （nMOSFETs） are fabricated by using these In0.53Ga0.47As-OI structures with excellent electrical characteristics. Positive bias temperature instability （PBTI） and hot carrier injection （HCI） characterizations are performed for the In0.53Ga0.47As-OI nMOSFETs. It is confirmed that the In0.53Ga0.47 As-OI nMOSFETs with a thinner body thickness suffer from more severe degradations under both PBTI and HCr stresses. Moreover, the different evolutions of the threshold voltage and the saturation current of the UTB In0.53Ga0.47As-OI nMOSFETs may be due to the slow border traps.

A high voltage silicon-on-insulator lateral insulated gate bipolar transistor with a reduced cell-pitch

A high voltage（〉 600 V） integrable silicon-on-insulator（SOI） trench-type lateral insulated gate bipolar transistor（LIGBT） with a reduced cell-pitch is proposed.The LIGBT features multiple trenches（MTs）：two oxide trenches in the drift region and a trench gate extended to the buried oxide（BOX）.Firstly,the oxide trenches enhance electric field strength because of the lower permittivity of oxide than that of Si.Secondly,oxide trenches bring in multi-directional depletion,leading to a reshaped electric field distribution and an enhanced reduced-surface electric-field（RESURF） effect.Both increase the breakdown voltage（BV）.Thirdly,oxide trenches fold the drift region around the oxide trenches,leading to a reduced cell-pitch.Finally,the oxide trenches enhance the conductivity modulation,resulting in a high electron/hole concentration in the drift region as well as a low forward voltage drop（Von）.The oxide trenches cause a low anode-cathode capacitance,which increases the switching speed and reduces the turn-off energy loss（Eoff）.The MT SOI LIGBT exhibits a BV of 603 V at a small cell-pitch of 24 μm,a Von of 1.03 V at 100 A/cm-2,a turn-off time of 250 ns and Eoff of 4.1×10？3 mJ.The trench gate extended to BOX synchronously acts as dielectric isolation between high voltage LIGBT and low voltage circuits,simplifying the fabrication processes.

Optimization of ambipolar current and analog/RF performance for T-shaped tunnel field-effect transistor with gate dielectric spacer

A new T-shaped tunnel field-effect transistor(TTFET) with gate dielectric spacer(GDS) structure is proposed in this paper. To further studied the effects of GDS structure on the TTFET, detailed device characteristics such as current-voltage relationships, energy band diagrams, band-to-band tunneling(BTBT) rate and the magnitude of the electric field are investigated by using TCAD simulation. It is found that compared with conventional TTFET and TTFET with gate-drain overlap(GDO) structure, GDS-TTFET not only has the minimum ambipolar current but also can suppress the ambipolar current under a more extensive bias range. Furthermore, the analog/RF performances of GDS-TTFET are also investigated in terms of transconductance, gate-source capacitance, gate-drain capacitance, cutoff frequency, and gain bandwidth production. By inserting a low-κ spacer layer between the gate electrode and the gate dielectric, the GDS structure can effectively reduce parasitic capacitances between the gate and the source/drain, which leads to better performance in term of cutoff frequency and gain bandwidth production. Finally, the thickness of the gate dielectric spacer is optimized for better ambipolar current suppression and improved analog/RF performance.

Double-gate tunnel field-effect transistor:Gate threshold voltage modeling and extraction

The tunnel field-effect transistor(TFET) is a potential candidate for the post-CMOS era.As one of the most important electrical parameters of a device,double gate TFET(DG-TFET) gate threshold voltage was studied.First,a numerical simulation study of transfer characteristic and gate threshold voltage in DG-TFET was reported.Then,a simple analytical model for DG-TFET gate threshold voltage VTG was built by solving quasi-two-dimensional Poisson equation in Si film.The model as a function of the drain voltage,the Si layer thickness,the gate length and the gate dielectric was discussed.It is shown that the proposed model is consistent with the simulation results.This model should be useful for further investigation of performance of circuits containing TFETs.

Low-Frequency Noise in Gate Tunable Topological Insulator Nanowire Field Emission Transistor near the Dirac Point

Low-frequency flicker noise is usually associated with material defects or imperfection of fabrication procedure. Up to now, there is only very limited knowledge about flicker noise of the topological insulator, whose topologically protected conducting surface is theoretically immune to back scattering. To suppress the bulk conductivity we synthesize antimony doped Bi2Se3 nanowires and conduct transport measurements at cryogenic temperatures. The low-frequency current noise measurement shows that the noise amplitude at the high-drain current regime can be described by Hooge＇s empirical relationship, while the noise level is significantly lower than that predicted by Hooge＇s model near the Dirac point. Furthermore, different frequency responses of noise power spectrum density for specific drain currents at the low drain current regime indicate the complex origin of noise sources of topological insulator.

Two-dimensional threshold voltage model of a nanoscale silicon-on-insulator tunneling field-effect transistor

The tunneling field-effect transistor（TFET） is a potential candidate for the post-CMOS era.In this paper,a threshold voltage model is developed for this new kind of device.First,two-dimensional（2D） models are used to describe the distributions of potential and electric field in the channel and two depletion regions.Then based on the physical definition of threshold voltage for the nanoscale TFET,the threshold voltage model is developed.The accuracy of the proposed model is verified by comparing the calculated results with the 2D device simulation data.It has been demonstrated that the effects of varying the device parameters can easily be investigated using the model presented in this paper.This threshold voltage model provides a valuable reference to TFET device design,simulation,and fabrication.

Heteromaterial-gate line tunnel field-effect transistor based on Si/Ge heterojunction

A Si/Ge heterojunction line tunnel field-effect transistor （LTFET） with a symmetric heteromaterial gate is proposed. Compared to single-material-gate LTFETs, the heteromaterial gate LTFET shows an off-state leakage current that is three orders of magnitude lower, and steeper subthreshold characteristics, without degradation in the on-state current. We reveal that these improvements are due to the induced local potential barrier, which arises from the energy-band profile modulation effect. Based on this novel structure, the impacts of the physical parameters of the gap region between the pocket and the drain, including the work-function mismatch between the pocket gate and the gap gate, the type of dopant, and the doping concentration, on the device performance are investigated. Simulation and theoretical calculation results indicate that the gap gate material and n-type doping level in the gap region should be optimized simultaneously to make this region fully depleted for further suppression of the off-state leakage current.

Low-Frequency Noise in Amorphous Indium Zinc Oxide Thin Film Transistors with Aluminum Oxide Gate Insulator

Low-frequency noise（LFN） in all operation regions of amorphous indium zinc oxide（a-IZO） thin film transistors（TFTs） with an aluminum oxide gate insulator is investigated. Based on the LFN measured results, we extract the distribution of localized states in the band gap and the spatial distribution of border traps in the gate dielectric,and study the dependence of measured noise on the characteristic temperature of localized states for a-IZO TFTs with Al2 O3 gate dielectric. Further study on the LFN measured results shows that the gate voltage dependent noise data closely obey the mobility fluctuation model, and the average Hooge＇s parameter is about 1.18×10^-3.Considering the relationship between the free carrier number and the field effect mobility, we simulate the LFN using the △N-△μ model, and the total trap density near the IZO/oxide interface is about 1.23×10^18 cm^-3eV^-1.

Improved Performance of Organic Thin Film Transistor with an Inorganic Oxide/Polymer Double-Layer Insulator

We employ the Ta2Os/PVP （poly-4-vinylphenol） double-layer gate insulator to improve the performance of pentacene thin-film transistors. It is found that the double-layer insulator has low leakage current, smooth surface and considerably high capacitance. Compared to Ta205 insulator layers, the device with the Ta2Os/PVP doublelayer insulator exhibits an enhancement of the field-effect mobility from 0.21 to 0.54 cm2/Vs, and the decreasing threshold voltage from 4.38 V to -2.5 V. The results suggest that the Ta2Os/PVP double-layer insulator is a potential gate insulator for fabricating OTFTs with good electrical performance.

SiC gate-controlled bipolar field effect composite transistor with polysilicon region for improving on-state current

A novel silicon carbide gate-controlled bipolar field effect composite transistor with poly silicon region(SiC GCBTP)is proposed.Different from the traditional electrode connection mode of SiC vertical diffused MOS(VDMOS),the P+region of P-well is connected with the gate in SiC GCBTP,and the polysilicon region is added between the P+region and the gate.By this method,additional minority carriers can be injected into the drift region at on-state,and the distribution of minority carriers in the drift region will be optimized,so the on-state current is increased.In terms of static characteristics,it has the same high breakdown voltage(811 V)as SiC VDMOS whose length of drift is 5.5μm.The on-state current of SiC GCBTP is 2.47×10^(-3)A/μm(V_(G)=10 V,V_(D)=10 V)which is 5.7 times of that of SiC IGBT and 36.4 times of that of SiC VDMOS.In terms of dynamic characteristics,the turn-on time of SiC GCBTP is only 0.425 ns.And the turn-off time of SiC GCBTP is similar to that of SIC insulated gate bipolar transistor(IGBT),which is 114.72 ns.

Sensing with extended gate negative capacitance ferroelectric field-effect transistors

With major signal analytical elements situated away from the measurement environment,extended gate(EG)ion-sensitive fieldeffect transistors(ISFETs)offer prospects for whole chip circuit design and system integration of chemical sensors.In this work,a highly sensitive and power-efficient ISFET was proposed based on a metal-ferroelectric-insulator gate stack with negative capacitance–induced super-steep subthreshold swing and ferroelectric memory function.Along with a remotely connected EG electrode,the architecture facilitates diverse sensing functions for future establishment of smart biochemical sensor platforms.

Ultralow turnoff loss dual-gate SOI LIGBT with trench gate barrier and carrier stored layer

A novel ultralow turnoff loss dual-gate silicon-on-insulator （SOI） lateral insulated gate bipolar transistor （LIGBT） is proposed. The proposed SOI LIGBT features an extra trench gate inserted between the p-well and n-drift, and an n-type carrier stored （CS） layer beneath the p-well. In the on-state, the extra trench gate acts as a barrier, which increases the cartier density at the cathode side of n-drift region, resulting in a decrease of the on-state voltage drop （Von）. In the off-state, due to the uniform carder distribution and the assisted depletion effect induced by the extra trench gate, large number of carriers can be removed at the initial turnoff process, contributing to a low turnoff loss （Eoff）. Moreover, owing to the dual-gate field plates and CS layer, the carrier density beneath the p-well can greatly increase, which further improves the tradeoff between Eoff and Von. Simulation results show that Eoff of the proposed SOI LIGBT can decrease by 77% compared with the conventional trench gate SOI LIGBT at the same Von of 1.1 V.

Extended-source broken gate tunnel FET for improving direct current and analog/radio-frequency performance

The various advantages of extended-source(ES),broken gate(BG),and hetero-gate-dielectric(HGD)technology are blended together for the proposed tunnel field-effect transistor(ESBG TFET)in order to enhance the direct-current and analog/radio-frequency performance.The source of the ESBG TFET is extended into channel for the purpose of increasing the point and line tunneling in the device at the tunneling junction,and then,the on-state current for the ESBG TFET increases.The influence of the source region length on the direct-current and radio-frequency performance parameters of the ESBG TFET is analyzed in detail.The results show that the proposed TFET exhibits a high on-state current to off-state current ratio of 1013,large transconductance of 1200μS/μm,high cut-off frequency of 72.8 GHz,and high gain bandwidth product of 14.3 GHz.Apart from these parameters,the ESBG TFET also demonstrates high linearity distortion parameters in terms of the second-and third-order voltage intercept points,the third-order input interception point,and the third-order intermodulation distortion.Therefore,the ESBG TFET greatly promotes the application potential of conventional TFETs.

Gate leakage current of NMOSFET with ultra-thin gate oxide

As dimensions of the metal-oxide-semiconductor field-effect transistor (MOSFET) are scaling down and the thickness of gate oxide is decreased,the gate leakage becomes more and more prominent and has been one of the most important limiting factors to MOSFET and circuits lifetime.Based on reliability theory and experiments,the direct tunneling current in lightly-doped drain (LDD) NMOSFET with 1.4 nm gate oxide fabricated by 90 nm complementary metal oxide semiconductor (CMOS) process was studied in depth.High-precision semiconductor parameter analyzer was used to conduct the tests.Law of variation of the direct tunneling (DT) current with channel length,channel width,measuring voltage,drain bias and reverse substrate bias was revealed.The results show that the change of the DT current obeys index law;there is a linear relationship between gate current and channel dimension;drain bias and substrate bias can reduce the gate current.

Improving dynamic characteristics for IGBTs by using interleaved trench gate

A novel trench insulated gate bipolar transistor(IGBT) with improved dynamic characteristics is proposed and investigated. The poly gate and poly emitter of the proposed IGBT are arranged alternately along the trench. A self-biased p-MOSFET is formed on the emitter side. Owing to this unique three-dimensional(3D) trench architecture, both the turnoff characteristic and the turn-on characteristic can be greatly improved. At the turn-off moment, the maximum electric field and impact ionization rate of the proposed IGBT decrease and the dynamic avalanche(DA) is suppressed. Comparing with the carrier-stored trench gate bipolar transistor(CSTBT), the turn-off loss(E_(off)) of the proposed IGBT also decreases by 31% at the same ON-state voltage. At the turn-on moment, the built-in p-MOSFET reduces the reverse displacement current(I_(G_dis)), which is conducive to lowing dI_(C)/d_(t). As a result, compared with the CSTBT with the same turn-on loss(E_(on)), at I_(C) = 20 A/cm^(2), the proposed IGBT decreases by 35% of collector surge current(I_(surge)) and 52% of dI_(C)/d_(t).

Negative Resistance Region 10 nm Gate Length on FINFET

In this paper the physical characteristics of FINFET (fin-field effect transistor) transistor behavior are investigated. For the analysis, semi-classical electron transfer method was used based on drift diffusion approximation by TCAD (Tiber CAD) software. Simulations show that the output resistance of FINFET along very small gate (gate length and fin height of 50 nm) is negative. The negative resistance is used in oscillators.

基于注意力机制的CNN-BiLSTM的IGBT剩余使用寿命预测

针对绝缘栅双极型晶体管(IGBT)可靠性问题,提出了一种融合卷积神经网络(CNN)、双向长短期记忆(BiLSTM)网络和注意力机制的剩余使用寿命(RUL)预测模型,可用于IGBT的寿命预测。模型中使用CNN提取特征参数,BiLSTM提取时序信息,注意力机制加权处理特征参数。使用IGBT加速老化数据集对提出的模型进行验证。结果表明,对比自回归差分移动平均(ARIMA)、长短期记忆(LSTM)、多层LSTM(Multi-LSTM)、 BiLSTM预测模型,在均方根误差和决定系数等评价指标方面该模型的性能最优。验证了提出的寿命预测模型对IGBT失效预测是有效的。