Development of 8-inch Key Processes for Insulated-Gate Bipolar Transistor

Based on the construction of the 8-inch fabricat ion line, advanced process technology of 8-inch wafer, as well as the fourth-generation high-voltage double-diffused metal-oxide semiconductor(DMOS+) insulated-gate bipolar transistor(IGBT) technology and the fifth-generation trench gate IGBT technology, have been developed, realizing a great-leap forward technological development for the manufacturing of high-voltage IGBT from 6-inch to 8-inch. The 1600 A/1.7 kV and 1500 A/3.3 kV IGBT modules have been successfully fabricated, qualified, and applied in rail transportation traction system.

SiC gate-controlled bipolar field effect composite transistor with polysilicon region for improving on-state current

A novel silicon carbide gate-controlled bipolar field effect composite transistor with poly silicon region(SiC GCBTP)is proposed.Different from the traditional electrode connection mode of SiC vertical diffused MOS(VDMOS),the P+region of P-well is connected with the gate in SiC GCBTP,and the polysilicon region is added between the P+region and the gate.By this method,additional minority carriers can be injected into the drift region at on-state,and the distribution of minority carriers in the drift region will be optimized,so the on-state current is increased.In terms of static characteristics,it has the same high breakdown voltage(811 V)as SiC VDMOS whose length of drift is 5.5μm.The on-state current of SiC GCBTP is 2.47×10^(-3)A/μm(V_(G)=10 V,V_(D)=10 V)which is 5.7 times of that of SiC IGBT and 36.4 times of that of SiC VDMOS.In terms of dynamic characteristics,the turn-on time of SiC GCBTP is only 0.425 ns.And the turn-off time of SiC GCBTP is similar to that of SIC insulated gate bipolar transistor(IGBT),which is 114.72 ns.

Temperature dependence of single-event transients in SiGe heterojunction bipolar transistors for cryogenic applications

We experimentally demonstrate that the dominant mechanism of single-event transients in silicon-germanium heterojunction bipolar transistors(SiGe HBTs)can change with decreasing temperature from+20℃to-180℃.This is accomplished by using a new well-designed cryogenic experimental system suitable for a pulsed-laser platform.Firstly,when the temperature drops from+20℃to-140℃,the increased carrier mobility drives a slight increase in transient amplitude.However,as the temperature decreases further below-140℃,the carrier freeze-out brings about an inflection point,which means the transient amplitude will decrease at cryogenic temperatures.To better understand this result,we analytically calculate the ionization rates of various dopants at different temperatures based on Altermatt's new incomplete ionization model.The parasitic resistivities with temperature on the charge-collection pathway are extracted by a two-dimensional(2D)TCAD process simulation.In addition,we investigate the impact of temperature on the novel electron-injection process from emitter to base under different bias conditions.The increase of the emitter-base junction's barrier height at low temperatures could suppress this electron-injection phenomenon.We have also optimized the built-in voltage equations of a high current compact model(HICUM)by introducing the impact of incomplete ionization.The present results and methods could provide a new reference for effective evaluation of single-event effects in bipolar transistors and circuits at cryogenic temperatures,and could provide a new evidence of the potential of SiGe technology in applications in extreme cryogenic environments.

High performance carrier stored trench bipolar transistor with dual shielding structure

We propose a novel high performance carrier stored trench bipolar transistor(CSTBT)with dual shielding structure(DSS-CSTBT).The proposed DSS-CSTBT features a double trench structure with different trench profiles in the surface,in which a shallow gate trench is shielded by a deep emitter trench and a thick oxide layer under it.Compared with the conventional CSTBT(con-CSTBT),the proposed DSS-CSTBT not only alleviates the negative impact of the shallow gate trench and highly doped CS layer on the breakdown voltage(BV),but also well reduces the gate-collector capacitance CGC,gate charge Q_(G),and turn-off loss E_(OFF)of the device.Furthermore,lower turn-on loss E_(ON)and gate drive loss E_(DR)are also obtained.Simulation results show that with the same CS layer doping concentration N_(CS)=1.5×10^(16)cm^(-3),the BV increases from 1312 V of the con-CSTBT to 1423 V of the proposed DSS-CSTBT with oxide layer thickness under gate(T_(og2))of 1μm.Moreover,compared with the con-CSTBT,the C_(GC)at V_(CE)of 25 V and miller plateau charge(Q_(GC))for the proposed DSS-CSTBT with T_(og2)of 1μm are reduced by 79.4%and 74.3%,respectively.With the VGEincreases from 0 V to 15 V,the total QGfor the proposed DSS-CSTBT with T_(og2)of 1μm is reduced by 49.5%.As a result,at the same on-state voltage drop(V_(CEON))of 1.55 V,the E_(ON)and E_(OFF)are reduced from 20.3 mJ/cm^(2)and 19.3 mJ/cm^(2)for the con-CSTBT to8.2 mJ/cm^(2)and 9.7 mJ/cm^(2)for the proposed DSS-CSTBT with T_(og2)of 1μm,respectively.The proposed DSS-CSTBT not only significantly improves the trade-off relationship between the V_(CEON)and E_(OFF)but also greatly reduces the E_(ON).

Sensitivity study of the SiGe heterojunction bipolar transistor single event effect based on pulsed laser and technology computer-aided design simulation

The single event effect of a silicon–germanium heterojunction bipolar transistor(SiGe HBT) was thoroughly investigated. By considering the worst bias condition, the sensitive area of the proposed device was scanned with a pulsed laser.With variation of the collector bias and pulsed laser incident energy, the single event transient of the SiGe HBT was studied.Moreover, the single event transient produced by laser irradiation at a wavelength of 532 nm was more pronounced than at a wavelength of 1064 nm. Finally, the impact of the equivalent linear energy transfer of the 1064 nm pulsed laser on the single event transient was qualitatively examined by performing technology computer-aided design simulations, and a good consistency between the experimental data and the simulated outcomes was attained.

Microwave damage susceptibility trend of a bipolar transistor as a function of frequency

We conduct a theoretical study of the damage susceptibility trend of a typical bipolar transistor induced by a high-power microwave （HPM） as a function of frequency. The dependences of the burnout time and the damage power on the signal frequency are obtained. Studies of the internal damage process and the mechanism of the device are carried out from the variation analysis of the distribution of the electric field, current density, and temperature. The investigation shows that the burnout time linearly depends on the signal frequency. The current density and the electric field at the damage position decrease with increasing frequency. Meanwhile, the temperature elevation occurs in the area between the p-n junction and the n n＋ interface due to the increase of the electric field. Adopting the data analysis software, the relationship between the damage power and frequency is obtained. Moreover, the thickness of the substrate has a significant effect on the burnout time.

A novel high-voltage light punch-through carrier stored trench bipolar transistor with buried p-layer

A novel high-voltage light punch-through（LPT） carrier stored trench bipolar transistor（CSTBT） with buried p-layer（BP） is proposed in this paper.Since the negative charges in the BP layer modulate the bulk electric field distribution,the electric field peaks both at the junction of the p base/n-type carrier stored（N-CS） layer and the corners of the trench gates are reduced,and new electric field peaks appear at the junction of the BP layer/N drift region.As a result,the overall electric field in the N drift region is enhanced and the proposed structure improves the breakdown voltage（BV） significantly compared with the LPT CSTBT.Furthermore,the proposed structure breaks the limitation of the doping concentration of the N-CS layer（NN CS） to the BV,and hence a higher NN CS can be used for the proposed LPT BP-CSTBT structure and a lower on-state voltage drop（Vce（sat）） can be obtained with almost constant BV.The results show that with a BP layer doping concentration of NBP = 7 × 10^15 cm^-3,a thickness of LBP = 2.5 μm,and a width of WBP = 5 μm,the BV of the proposed LPT BP-CSTBT increases from 1859 V to 1862 V,with NN CS increasing from 5 × 10^15 cm^-3 to 2.5 × 10^16 cm^-3.However,with the same N-drift region thickness of 150 μm and NN CS,the BV of the CSTBT decreases from 1598 V to 247 V.Meanwhile,the Vce（sat） of the proposed LPT BP-CSTBT structure decreases from 1.78 V to 1.45 V with NN CS increasing from 5 × 10^15 cm^-3 to 2.5 × 10^16 cm^-3.

Hardening measures for bipolar transistors against microwave-induced damage

In the present paper we study the influences of the bias voltage and the external components on the damage progress of a bipolar transistor induced by high-power microwaves. The mechanism is presented by analyzing the variation in the internal distribution of the temperature in the device. The findings show that the device becomes less vulnerable to damage with an increase in bias voltage. Both the series diode at the base and the relatively low series resistance at the emitter, Re, can obviously prolong the burnout time of the device. However, Re will aid damage to the device when the value is sufficiently high due to the fact that the highest hot spot shifts from the base-emitter junction to the base region. Moreover, the series resistance at the base Rb will weaken the capability of the device to withstand microwave damage.

Effects of microwave pulse-width damage on a bipolar transistor

This paper presents a theoretical study of the pulse-width effects on the damage process of a typical bipolar transistor caused by high power microwaves（HPMs） through the injection approach.The dependences of the microwave damage power,P,and the absorbed energy,E,required to cause the device failure on the pulse width τ are obtained in the nanosecond region by utilizing the curve fitting method.A comparison of the microwave pulse damage data and the existing dc pulse damage data for the same transistor is carried out.By means of a two-dimensional simulator,ISE-TCAD,the internal damage processes of the device caused by microwave voltage signals and dc pulse voltage signals are analyzed comparatively.The simulation results suggest that the temperature-rising positions of the device induced by the microwaves in the negative and positive half periods are different,while only one hot spot exists under the injection of dc pulses.The results demonstrate that the microwave damage power threshold and the absorbed energy must exceed the dc pulse power threshold and the absorbed energy,respectively.The dc pulse damage data may be useful as a lower bound for microwave pulse damage data.

Two-dimensional analysis of the interface state effect on current gain for a 4H-SiC bipolar junction transistor

This paper studies two-dimensional analysis of the surface state effect on current gain for a 4H-SiC bipolar junction transistor （BJT）. Simulation results indicate the mechanism of current gain degradation, which is surface Fermi level pinning leading to a strong downward bending of the energy bands to form the channel of surface electron recombination current. The experimental results are well-matched with the simulation, which is modeled by exponential distributions of the interface state density replacing the single interface state trap. Furthermore, the simulation reveals that the oxide quality of the base emitter junction interface is very important for 4H-SiC BJT performance.

Machine learning-based analyses for total ionizing dose effects in bipolar junction transistors

Machine learning methods have proven to be powerful in various research fields.In this paper,we show that research on radiation effects could benefit from such methods and present a machine learning-based scientific discovery approach.The total ionizing dose(TID)effects usually cause gain degradation of bipolar junction transistors(BJTs),leading to functional failures of bipolar integrated circuits.Currently,many experiments of TID effects on BJTs have been conducted at different laboratories worldwide,producing a large amount of experimental data which provides a wealth of information.However,it is difficult to utilize these data effectively.In this study,we proposed a new artificial neural network(ANN)approach to analyze the experimental data of TID effects on BJTs An ANN model was built and trained using data collected from different experiments.The results indicate that the proposed ANN model has advantages in capturing nonlinear correlations and predicting the data.The trained ANN model suggests that the TID hardness of a BJT tends to increase with base current I.A possible cause for this finding was analyzed and confirmed through irradiation experiments.

Comparison of total dose effects on SiGe heterojunction bipolar transistors induced by different swift heavy ion irradiation

The degradations in NPN silicon-germanium （SiGe） heterojunction bipolar transistors （HBTs） were fully studied in this work, by means of 25-MeV Si, 10-MeV C1, 20-MeV Br, and 10-MeV Br ion irradiation, respectively. Electrical parameters such as the base current （IB）, current gain （β）, neutral base recombination （NBR）, and Early voltage （VA） were investigated and used to evaluate the tolerance to heavy ion irradiation. Experimental results demonstrate that device degradations are indeed radiation-source-dependent, and the larger the ion nuclear energy loss is, the more the displacement damages are, and thereby the more serious the performance degradation is. The maximum degradation was observed in the transistors irradiated by 10-MeV Br. For 20-MeV and 10-MeV Br ion irradiation, an unexpected degradation in Ic was observed and Early voltage decreased with increasing ion fluence, and NBR appeared to slow down at high ion fluence. The degradations in SiGe HBTs were mainly attributed to the displacement damages created by heavy ion irradiation in the transistors. The underlying physical mechanisms are analyzed and investigated in detail.

Analysis of displacement damage effects on bipolar transistors irradiated by spallation neutrons

Displacement damage induced by neutron irradiation in China Spallation Neutron Source(CSNS) is studied on bipolar transistors with lateral PNP, substrate PNP, and vertical NPN configurations, respectively. Comparison of the effects on different type transistors is conducted based on displacement damage factor, and the differences are analyzed through minority carrier lifetime calculation and structure analysis. The influence of CSNS neutrons irradiation on the lateral PNP transistors is analyzed by the gate-controlled method, including the oxide charge accumulation, surface recombine velocity,and minority carrier lifetime. The results indicate that the total ionizing dose in CSNS neutron radiation environment is negligible in this study. The displacement damage factors based on 1-MeV equivalent neutron flux of different transistors are consistent between Xi’an pulse reactor(XAPR) and CSNS.

Early effect modeling of silicon-on-insulator SiGe heterojunction bipolar transistors

Silicon germanium （SiGe） heterojunction bipolar transistor （HBT） on thin silicon-on-insulator （SOI） has recently been demonstrated and integrated into the latest SOI BiCMOS technology. The Early effect of the SOI SiGe HBT is analysed considering vertical and horizontal collector depletion, which is different from that of a bulk counterpart. A new compact formula of the Early voltage is presented and validated by an ISE TCAD simulation. The Early voltage shows a kink with the increase of the reverse base-collector bias. Large differences are observed between SOI devices and their bulk counterparts. The presented Early effect model can be employed for a fast evaluation of the Early voltage and is useful to the design, the simulation and the fabrication of high performance SOI SiCe devices and circuits.

Thermal stability improvement of a multiple finger power SiGe heterojunction bipolar transistor under different power dissipations using non-uniform finger spacing

A method of non-uniform finger spacing is proposed to enhance thermal stability of a multiple finger power SiGe heterojunction bipolar transistor under different power dissipations. Temperature distribution on the emitter fingers of a multi-finger SiGe heterojunction bipolar transistor is studied using a numerical electro-thermal model. The results show that the SiGe heterojunction bipolar transistor with non-uniform finger spacing has a small temperature difference between fingers compared with a traditional uniform finger spacing heterojunction bipolar transistor at the same power dissipation. What is most important is that the ability to improve temperature non-uniformity is not weakened as power dissipation increases. So the method of non-uniform finger spacing is very effective in enhancing the thermal stability and the power handing capability of power device. Experimental results verify our conclusions.

Analytical base collector depletion capacitance in vertical SiGe heterojunction bipolar transistors fabricated on CMOS-compatible silicon on insulator

The base-collector depletion capacitance for vertical SiGe npn heterojunction bipolar transistors （HBTs） on silicon on insulator （SOI） is split into vertical and lateral parts. This paper proposes a novel analytical depletion capacitance model of this structure for the first time. A large discrepancy is predicted when the present model is compared with the conventional depletion model, and it is shown that the capacitance decreases with the increase of the reverse collector- base bias-and shows a kink as the reverse collector-base bias reaches the effective vertical punch-through voltage while the voltage differs with the collector doping concentrations, which is consistent with measurement results. The model can be employed for a fast evaluation of the depletion capacitance of an SOI SiGe HBT and has useful applications on the design and simulation of high performance SiGe circuits and devices.

Substrate bias effects on collector resistance in SiGe heterojunction bipolar transistors on thin film silicon-on-insulator

An analytical expression for the co/lector resistance of a novel vertical SiGe heterojunction bipolar transistor （HBT） on thin film silicon-on-insulator （SOI） is obtained with the substrate bias effects being considered. The resistance is found to decrease slowly and then quickly and to have kinks with the increase of the substrate-collector bias, which is quite different from that of a conventional bulk HBT. The model is consistent with the simulation result and the reported data and is useful to the frequency characteristic design of 0.13 μtm millimeter-wave SiGe SOI BiCMOS devices.

Radiation-induced 1/f noise degradation of PNP bipolar junction transistors at different dose rates

It is found that ionizing-radiation can lead to the base current and the 1/f noise degradations in PNP bipolar junction transistors. In this paper, it is suggested that the surface of the space charge region of the emitter-base junction is the main source of the base surface 1/f noise. A model is developed which identifies the parameters and describes their interactive contributions to the recombination current at the surface of the space charge region. Based on the theory of carrier number fluctuation and the model of surface recombination current, a 1/f noise model is developed. This model suggests that 1/f noise degradations are the result of the accumulation of oxide-trapped charges and interface states. Combining models of ELDRS, this model can explain the reason why the 1/f noise degradation is more severe at a low dose rate than at a high dose rate. The radiations were performed in a Co60 source up to a total dose of 700 Gy（Si）. The low dose rate was 0.001 Gy（Si）/s and the high dose rate was 0.1 Gy（Si）/s. The model accords well with the experimental results.

A dual-gate and dielectric-inserted lateral trench insulated gate bipolar transistor on a silicon-on-insulator substrate

In this paper, a novel dual-gate and dielectric-inserted lateral trench insulated gate bipolar transistor （DGDI LTIGBT） structure, which features a double extended trench gate and a dielectric inserted in the drift region, is proposed and discussed. The device can not only decrease the specific on-resistance Ron,sp , but also simultaneously improve the temperature performance. Simulation results show that the proposed LTIGBT achieves an ultra-low on-state voltage drop of 1.31 V at 700 A·cm-2 with a small half-cell pitch of 10.5 μm, a specific on-resistance R on,sp of 187 mΩ·mm2, and a high breakdown voltage of 250 V. The on-state voltage drop of the DGDI LTIGBT is 18% less than that of the DI LTIGBT and 30.3% less than that of the conventional LTIGBT. The proposed LTIGBT exhibits a good positive temperature coefficient for safety paralleling to handling larger currents and enhances the short-circuit capability while maintaining a low self-heating effect. Furthermore, it also shows a better tradeoff between the specific on-resistance and the turnoff loss, although it has a longer turnoff delay time.

A G-band terahertz monolithic integrated amplifier in 0.5-μm InP double heterojunction bipolar transistor technology

Design and characterization of a G-band（140–220 GHz） terahertz monolithic integrated circuit（TMIC） amplifier in eight-stage common-emitter topology are performed based on the 0.5-μm In Ga As/In P double heterojunction bipolar transistor（DHBT）. An inverted microstrip line is implemented to avoid a parasitic mode between the ground plane and the In P substrate. The on-wafer measurement results show that peak gains are 20 dB at 140 GHz and more than 15-dB gain at 140–190 GHz respectively. The saturation output powers are-2.688 dBm at 210 GHz and-2.88 dBm at 220 GHz,respectively. It is the first report on an amplifier operating at the G-band based on 0.5-μm InP DHBT technology. Compared with the hybrid integrated circuit of vacuum electronic devices, the monolithic integrated circuit has the advantage of reliability and consistency. This TMIC demonstrates the feasibility of the 0.5-μm InGaAs/InP DHBT amplifier in G-band frequencies applications.