Large Eddy Simulation Study on the Turbulence and Flame Characteristics under Analogical Integral Scale and Turbulence Intensity of Turbulent Premixed Flames

Bunsen burner is a typical geometry for investigating the turbulence-flame interaction.In most experimental studies,only turbulence intensity u′and integral scale l0 are used to characterize the turbulent flow field,regardless of the perforation geometry of perforated plates.However,since the geometry influences the developing process and vortex broken,the plate geometry has to be considered when discussing the flame-turbulence interaction.In order to investigate conditions at the same l0 and u′using different geometries,large eddy simulation of CH_(4)/air flames with dynamic TF combustion model was performed.The model validation shows good agreement between Large Eddy Simulation(LES)and experimental results.In the non-reacting flows,the Vortex Stretching of circular-perforated plate condition is always larger than that of slot-perforated plate condition,which comes from the stresses in the flow fields to stretch the vorticity vector.In reacting flows,at the root of the flame,the Vortex Stretching plays a major role,and the total vorticity here of circular-perforated plate condition is still larger(53.8%and 300%larger than that of the slot-perforated plate at x/D=0 and x/D=2.5,respectively).More small-scale vortex in circular-perforated plate condition can affect and wrinkle the flame front to increase the Probability Density Function(PDF)at large curvatures.The 3D curvature distributions of both cases bias to negative values.The negative trend of curvatures at the instant flame front results from the Dilatation term.Also,the value of the Vortex Stretching and the Dilatation at the flame front of circular-perforated plate condition is obviously larger.

Two-phase micro-and macro-time scales in particle-laden turbulent channel flows

The micro- and macro-time scales in two-phase turbulent channel flows are investigated using the direct nu- merical simulation and the Lagrangian particle trajectory methods for the fluid- and the particle-phases, respectively. Lagrangian and Eulerian time scales of both phases are cal- culated using velocity correlation functions. Due to flow anisotropy, micro-time scales are not the same with the theo- retical estimations in large Reynolds number （isotropic） tur- bulence. Lagrangian macro-time scales of particle-phase and of fluid-phase seen by particles are both dependent on particle Stokes number. The fluid-phase Lagrangian inte- gral time scales increase with distance from the wall, longer than those time scales seen by particles. The Eulerian inte- gral macro-time scales increase in near-wall regions but de- crease in out-layer regions. The moving Eulerian time scales are also investigated and compared with Lagrangian integral time scales, and in good agreement with previous measure- ments and numerical predictions. For the fluid particles the micro Eulerian time scales are longer than the Lagrangian ones in the near wall regions, while away from the walls the micro Lagrangian time scales are longer. The Lagrangian integral time scales are longer than the Eulerian ones. The results are useful for further understanding two-phase flow physics and especially for constructing accurate prediction models of inertial particle dispersion.

CALL FOR PAPERS Dec.2018 Special Issue on Large Scale Renewable Energy Integration

Guest Editor in Chief:Professor Xiao-Ping Zhang, University of Birmingham The potential for renewable energy to make contributions to mitigating the impact of climate change is expected to increase significantly in the longer term. Renewable energy generation technologies including onshore wind, offshore wind, wave,tidal, marine current, and ocean thermal energy generation as well as PV power generation, which are considered

A high-throughput VLSI design for JPEG2000 9/7 discrete wavelet transform

To achieve high parallel computation of discrete wavelet transform （DWT） in JPEG2000, a high-throughput two-dimensional （2D） 9/7 DWT very large scale integration （VLSI） design is proposed, in which the row processor is based on flipping structure. Due to the difference of the input data flow, the column processor is obtained by adding the input selector and data buffer to the row processor. Normalization steps in row and column DWT are combined to reduce the number of multipliers, and the rationality is verified. By rearranging the output of four-line row DWT with a multiplexer （MUX）, the amount of data processed by each column processor becomes half, and the four-input/four- output architecture is implemented. For an image with the size of N x N, the computing time of one-level 2D 9/7 DWT is 0.25N2 ＋ 1.5N clock cycles. The critical path delay is one multiplier delay, and only 5N internal memory is required. The results of post-route simulation on FPGA show that clock frequency reaches 136 MHz, and the throughput is 544 Msample/s, which satisfies the requirements of high-speed applications.

ASIC Design of Floating-Point FFT Processor

An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields. Several novel design techniques for floating-point adder and multiplier are introduced in detail to enhance the speed of the system. At the same time, the power consumption is decreased. The hardware area is effectively reduced as an improved butterfly processor is developed. There is a substantial increase in the performance of the design since a pipelined architecture is adopted, and very large scale integrated (VLSI) is easy to realize due to the regularity. A result of validation using field programmable gate array (FPGA) is shown at the end. When the system clock is set to 50 MHz, 204.8 μs is needed to complete the operation of FFT computation.

Reduced bit low power VLSI architectures for motion estimation

Low power and real time very large scale integration （VLSI） architectures of motion estimation （ME） algorithms for mobile devices and applications are presented. The power reduction is achieved by devising a novel correction recovery mechanism based on algorithms which allow the use of reduced bit sum of absolute difference （RBSAD） metric for calculating matching error and conversion to full resolution sum of absolute difference （SAD） metric whenever necessary. Parallel and pipelined architectures for high throughput of full search ME corresponding to both the full resolution SAD and the generalized RBSAD algorithm are synthe- sized using Xilinx Synthesis Tools （XST）, where the ME designs based on reduced bit （RB） algorithms demonstrate the reduction in power consumption up to 45% and/or the reduction in area up to 38%.

A Parallel-based Lifting Algorithm and VLSI Architecture for DWT

A novel Parallel-Based Lifting Algorithm （PBLA） for Discrete Wavelet Transform （DWT）, exploiting the parallelism of arithmetic operations in all lifting steps, is proposed in this paper. It leads to reduce the critical path latency of computation, and to reduce the complexity of hardware implementation as well. The detailed derivation on the proposed algorithm, as well as the resulting Very Large Scale Integration （VLSI） architecture, is introduced, taking the 9/7 DWT as an example but without loss of generality. In comparison with the Conventional Lifting Algorithm Based Implementation （CLABI）, the critical path latency of the proposed architecture is reduced by more than half from （4Tm ＋ 8Ta）to Tm ＋ 4Ta, and is competitive to that of Convolution-Based Implementation （CBI）, but the new implementation will save significantly in hardware. The experimental results demonstrate that the proposed architecture has good performance in both increasing working frequency and reducing area.

VLSI design of 3D display processing chip for binocular stereo displays

In order to develop the core chip supporting binocular stereo displays for head mounted display （HMD） and glasses-TV, a very large scale integrated （VISI） design scheme is proposed by using a pipeline architecture for 3D display processing chip （HMD100）. Some key techniques including stereo display processing and high precision video scaling based bicubic interpolation, and their hardware implementations which improve the image quality are presented. The proposed HMD100 chip is verified by the field-programmable gate array （FPGA）. As one of innovative and high integration SoC chips, HMD100 is designed by a digital and analog mixed circuit. It can support binocular stereo display, has better scaling effect and integration. Hence it is applicable in virtual reality （VR）, 3D games and other microdisplay domains.

RF-TSV DESIGN, MODELING AND APPLICATION FOR 3D MULTI-CORE COMPUTER SYSTEMS

The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient Through-Silicon Via (TSV) technology is critically important. In this paper, various Radio Frequency (RF) TSV designs and models are proposed. Specifically, the Cu-plug TSV with surrounding ground TSVs is used as the baseline structure. For further improvement, the dielectric coaxial and novel air-gap coaxial TSVs are introduced. Using the empirical parameters of these coaxial TSVs, the simulation results are obtained demonstrating that these coaxial RF-TSVs can provide two-order higher of cut-off frequencies than the Cu-plug TSVs. Based on these new RF-TSV technologies, we propose a novel 3D multi-core computer system as well as new architectures for manipulating the interfaces between RF and baseband circuit. Taking into consideration the scaling down of IC manufacture technologies, predictions for the performance of future generations of circuits are made. With simulation results indicating energy per bit and area per bit being reduced by 7% and 11% respectively, we can conclude that the proposed method is a worthwhile guideline for the design of future multi-core computer ICs.

Fault Detection and Test Response Compaction with Array of Two-Input Linear Logic

The design of space-efficient support hardware for built-in self-testing is of great significance in very large scale integration circuits and systems, particularly in view of the paradigm shift in recent times from system-on-board to system-on-chip technology. The subject paper proposes a new approach to designing aliasing-free or zero-aliasing space compaction hardware targeting specifically embedded cores-based system-on-chips for single stuck-line faults extending well-known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incomplete sequential machines. For a pair of response outputs of the circuit under test, the method introduces the notion of fault detection compatibility and conditional fault detection compatibility （conditional upon some other response output pair being simultaneously fault detection compatible） with respect to two-input XOR/XNOR logic. The process is illustrated with design details of space compressors for the International Symposium on Circuits and Systems or ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits using simulation programs ATALANTA and FSIM, attesting to the usefulness of the technique for its relative simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, thus making it suitable in commercial design environments.

Low-Power MCML Circuit with Sleep-Transistor

This paper proposes a low-power MOS current mode logic （MCML） circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage current. The 16× 16 bit parallel multiplier is designed with the proposed technology. Comparing with the previous MCML circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/258. This circuit is designed with Samsung 0.35 um complementary metal oxide semiconductor （CMOS） process. The validity and effectiveness are verified through the HSPICE simulation.

Low-Power Digital Circuit Design with Triple-Threshold Voltage

Triple-threshold CMOS technique provides the transistors that have low-, normal-, and high-threshold voltage. This paper describes a low-power carry look-ahead adder with triple-threshold CMOS technique. While the low-threshold voltage transistors are used to reduce the propagation delay time in the critical path, the high-threshold voltage transistors are used to reduce the power consumption in the shortest path. Comparing with the conventional CMOS circuit, the circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung 0.35 um CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

Architectural Design of 32 Bit Polar Encoder

The rapid development in the digital circuit design enhances the applications on very large scale integration era. Encoders are one among the digital circuits found in all communication systems. The polar encoding is mainly meant for its channel achieving property. It finds its application in communications, sensing and information theory. This coding proposed by Erdal Arikan is significant because of its zero error floors and simple architecture for hardware implementation. In this paper, a folded polar encoder is designed to start from the fully parallel architecture and proceeds with its data flow graph, delay requirement calculation, lifetime analysis and register allocation, which results in a very large scale integration architecture with minimum hardware utilization. The results are simulated for 4 and 8 parallel folded 32-bit polar encoder using Xilinx 14.6 ISIM and implemented in Virtex 5 field programmable gate array. A comparison is made on fully parallel and various folding techniques based on their resource utilization.

Design and Implementation of an Efficient Reversible Comparator Using TR Gate

Reversible logic is a new emerging technology with many promising applications in optical information processing, low power (Complementary Metal Oxide Semiconductor) CMOS design, (De Oxy RiboNucleic Acid) DNA computing, etc. In industrial automation, comparators play an important role in segregating faulty patterns from good ones. In previous works, these comparators have been implemented with more number of reversible gates and computational complexity. All these comparators use propagation technique to compare the data. This will reduce the efficiency of the comparators. To overcome the problem, this paper proposes an efficient comparator using (Thapliyal Ranganathan) TR gate utilizing full subtraction and half subtraction algorithm which will improve the computation efficiency. The comparator design using half subtraction algorithm shows an improvement in terms of quantum cost. The comparator design using full subtraction algorithm shows effectiveness in reducing number of reversible gates required and garbage output.

Novel Block Chain Technique for Data Privacy and Access Anonymity in Smart Healthcare

The Internet of Things (IoT) and Cloud computing are gaining popularity due to their numerous advantages, including the efficient utilization of internetand computing resources. In recent years, many more IoT applications have beenextensively used. For instance, Healthcare applications execute computations utilizing the user’s private data stored on cloud servers. However, the main obstaclesfaced by the extensive acceptance and usage of these emerging technologies aresecurity and privacy. Moreover, many healthcare data management system applications have emerged, offering solutions for distinct circumstances. But still, theexisting system has issues with specific security issues, privacy-preserving rate,information loss, etc. Hence, the overall system performance is reduced significantly. A unique blockchain-based technique is proposed to improve anonymityin terms of data access and data privacy to overcome the above-mentioned issues.Initially, the registration phase is done for the device and the user. After that, theGeo-Location and IP Address values collected during registration are convertedinto Hash values using Adler 32 hashing algorithm, and the private and publickeys are generated using the key generation centre. Then the authentication is performed through login. The user then submits a request to the blockchain server,which redirects the request to the associated IoT device in order to obtain thesensed IoT data. The detected data is anonymized in the device and stored inthe cloud server using the Linear Scaling based Rider Optimization algorithmwith integrated KL Anonymity (LSR-KLA) approach. After that, the Time-stamp-based Public and Private Key Schnorr Signature (TSPP-SS) mechanismis used to permit the authorized user to access the data, and the blockchain servertracks the entire transaction. The experimental findings showed that the proposedLSR-KLA and TSPP-SS technique provides better performance in terms of higherprivacy-preserving rate, lower information loss, execution time, and Central Processing Unit (CPU) usage than the existing techniques. Thus, the proposed method allows for better data privacy in the smart healthcare network.

The Effects of Turbulence Intensity and Tip Speed Ratio on the Coherent Structure of Horizontal-Axis Wind Turbine Wake:A Wind Tunnel Experiment

The evolution laws of the large-eddy coherent structure of the wind turbine wake have been evaluated via wind tunnel experiments under uniform and turbulent inflow conditions.The spatial correlation coefficients,the turbulence integral scales and power spectrum are obtained at different tip speed ratios(TSRs)based on the time-resolved particle image velocity(TR-PIV)technique.The results indicate that the large-eddy coherent structures are more likely to dissipate with an increase in turbulence intensity and TSR.Furthermore,the spatial correlation of the longitudinal pulsation velocity is greater than its axial counterpart,resulting into a wake turbulence dominated by the longitudinal pulsation.With an increase of turbulence intensity,the integral scale of the axial turbulence increases,meanwhile,its longitudinal counterpart decreases.Owing to an increase in TSR,the integral scale of axial turbulence decreases,whereas,that of the longitudinal turbulence increases.By analyzing the wake power spectrum,it is found that the turbulent pulsation kinetic energy of the wake structure is mainly concentrated in the low-frequency vortex region.The dissipation rate of turbulent kinetic energy increases with an increase of turbulence intensity and the turbulence is transported and dissipated on a smaller scale vortex,thus promoting the recovery of wake.

Effect of electric field on metallic SWCNT interconnects for nanoscale technologies

The influence of an electric field on metallic single walled carbon nanotube （SWCNT） interconnects is studied. A voltage-dependent equivalent circuit model is presented for the impedance parameters of single-wall carbon nanotubes that capture various electron-phonon scattering mechanisms as a function of the electric field. To estimate the performance of SWCNT bundle interconnects, signal delay and power dissipation are calculated based on the field dependent model that results in an improvement in the delay and power estimation accuracy compared to the field-independent model. We find that the power delay product of a SWCNT bundle increases with the increase in electric field but decreases with technology scaling showing that at a low electric field, the SWCNT bundle is a potential reliable alternative interconnect for future high performance VLSI industry at scaled technologies.

Effects of Dummy Thermal Vias on Interconnect Delay and Power Dissipation of Very Large Scale Integration Circuits

The interconnect temperature of very large scale integration（VLSI） circuits keeps rising due to self-heating and substrate temperature, which can increase the delay and power dissipation of interconnect wires. The thermal vias are regarded as a promising method to improve the temperature performance of VLSI circuits. In this paper, the extra thermal vias were used to decrease the delay and power dissipation of interconnect wires of VLSI circuits. Two analytical models were presented for interconnect temperature, delay and power dissipation with adding extra dummy thermal vias. The influence of the number of thermal vias on the delay and power dissipation of interconnect wires was analyzed and the optimal via separation distance was investigated. The experimental results show that the adding extra dummy thermal vias can reduce the interconnect average temperature, maximum temperature, delay and power dissipation. Moreover, this method is also suitable for clock signal wires with a large root mean square current.

Evaluation of criterion validity of CHF-quality of life scale of integrative medicine

Objective To evaluate the criterion validity of Chronic Heart Failure(CHF)-Quality of Life(QOL)Scale of Integrative Medicine(abbreviated as Scale).Methods Clinical data of 249 CHF in-patients were collected.

Wind Gust and Turbulence Statistics of Typhoons in South China

The wind data of four typhoons were obtained and analyzed. The wind speeds were measured by sonic anemometers at four observation sites in Guangdong and Hainan provinces. Detailed analysis of the wind data was conducted to investigate the turbulence characteristics of the typhoons. Characteristics of the gust factor and the turbulence integral scale of the typhoons were concluded with high confidence. The relationships among the gust factor, gust duration time, mean wind speed, roughness length, and turbulence intensity were described. The turbulence integral scale was found to be closely related to the segment length and turbulence intensity.