Development of a viable 3D integrated circuit technology

Three-dimensional integrated circuit technology with transistors stacked on top of one an-other in multi-layer silicon film has always been a vision in the future technology direction. While the idea is simple, the technique to obtain high performance multi-layer transistors is extraordinarily diffi-cult. Not until recently does such technology become feasible. In this paper, the background and vari-ous techniques to form three-dimensional circuits will be reviewed. Recent development of a simple and promising technology to achieve three-dimensional integration using Metal-Induced-Lateral-Crystalliza-tion will be described. Preliminary results of 3D inverters will also be provided to demonstrate the viabil-ity for 3D integration.

Development of 0.50μm CMOS Integrated Circuits Technology

Submicron CMOS IC technology, including triple layer resist lithography technology, RIE, LDD, Titanium Salicide, shallow junction, thin gate oxide, no bird's beak isolation and channel's multiple implantation doping technology have been developed. 0.50μm. CMOS integrated circuits have been fabricated using this submicron CMOS process.

Photonic integrated circuit components based on amorphous silicon-on-insulator technology

We present integrated-optic building blocks and functional photonic devices based on amorphous siliconon-insulator technology. Efficient deep-etched fiber-to-chip grating couplers, low-loss single-mode photonic wire waveguides, and compact power splitters are presented. Based on the sub-μm photonic wires, 2 × 2 Mach–Zehnder interferometers and add/drop microring resonators(MRRs) with low device footprints and high finesse up to 200 were realized and studied. Compact polarization rotators and splitters with ≥10 d B polarization extinction ratio were fabricated for the polarization management on-chip. The tuning and trimming capabilities of the material platform are demonstrated with efficient microheaters and a permanent device trimming method, which enabled the realization of energy-efficient photonic circuits. Wavelength multiplexers in the form of cascaded filter banks and 4 × 4 routers based on MRR switches are presented. Fabrication imperfections were analyzed and permanently corrected by an accurate laser-trimming method, thus enabling eight-channel multiplexers with record low metrics of sub-m W static power consumption and ≤1°C temperature overhead. The high quality of the functional devices, the high tuning efficiency, and the excellent trimming capabilities demonstrate the potential to realize low-cost, densely integrated, and ultralow-power 3D-stacked photonic circuits on top of CMOS microelectronics.

A monolithic K-band phase-locked loop for microwave radar application

A monolithic K-band phase-locked loop（PLL） for microwave radar application is proposed and implemented in this paper. By eliminating the tail transistor and using optimized high-Q LC-tank, the proposed voltage-controlled oscillator（VCO） achieves a tuning range of 18.4 to 23.3 GHz and reduced phase noise. Two cascaded current-mode logic（CML） divide-by-two frequency prescalers are implemented to bridge the frequency gap, in which inductor peaking technique is used in the first stage to further boost allowable input frequency.Six-stage TSPC divider chain is used to provide programmable division ratio from 64 to 127, and a second-order passive loop filter with 825 kHz bandwidth is also integrated on-chip to minimize required external components.The proposed PLL needs only approximately 18.2 μs settling time, and achieves a wide tuning range from 18.4 to 23.3 GHz, with a typical output power of –0.84 dBm and phase noise of 91：92 d Bc/Hz @ 1 MHz. The chip is implemented in TSMC 65 nm CMOS process, and occupies an area of 0.56 mm^2 without pads under a 1.2 V single voltage supply.

An investigation of the DC and RF performance of InP DHBTs transferred to RF CMOS wafer substrate

This paper investigated the DC and RF performance of the In P double heterojunction bipolar transistors（DHBTs）transferred to RF CMOS wafer substrate.The measurement results show that the maximum values of the DC current gain of a substrate transferred device had one emitter finger,of 0.8μm in width and 5μm in length,are changed unobviously,while the cut-off frequency and the maximum oscillation frequency are decreased from 220to 171 GHz and from 204 to 154 GHz,respectively.In order to have a detailed insight on the degradation of the RF performance,small-signal models for the In P DHBT before and after substrate transferred are presented and comparably extracted.The extracted results show that the degradation of the RF performance of the device transferred to RF CMOS wafer substrate are mainly caused by the additional introduced substrate parasitics and the increase of the capacitive parasitics induced by the substrate transfer process itself.