A compacted and low-offset low-power CMOS am- plifier for biosensor application is presented in this paper. It includes a low offset Op-Amp and a high precision current reference. With a novel continuous-time DC offse...A compacted and low-offset low-power CMOS am- plifier for biosensor application is presented in this paper. It includes a low offset Op-Amp and a high precision current reference. With a novel continuous-time DC offset rejection scheme, the IC achieves lower offset voltage and lower power consumption compared to previous designs. This configuration rejects large DC offset and drift that exist at the skin-electrode interface without the need of external components. The proposed amplifier has been implemented in SMIC 0.18-μm 1P6M CMOS technol-ogy, with an active silicon area of 100 μm by 120 μm. The back-annotated simulation results demonstrated the circuit features the systematic offset voltage less than 80 μV, the offset drift about 0.27 μV/℃ for temperature ranging from –30℃ to 100℃ and the total power dissipation consumed as low as 37.8 μW from a 1.8 V single supply. It dedicated to monitor low amplitude biomedical signals recording.展开更多
A double photodiode(PD) constructed by p^+/N-well junction and N-well/p-sub junction was designed and fabricated in a UMC 0.18-lm CMOS process. Based on the device structure and mechanism of double PD, a novel small-s...A double photodiode(PD) constructed by p^+/N-well junction and N-well/p-sub junction was designed and fabricated in a UMC 0.18-lm CMOS process. Based on the device structure and mechanism of double PD, a novel small-signal equivalent circuit model considering the carrier transit effect and the parasitic RC time constant was presented. By this model with complete electronic components, the double PD can be incorporated in a commercial circuit simulator. The component values were extracted by fitting the measured S-parameters using simulated annealing algorithm, and a good agreement between the measurement and the simulation results was achieved.展开更多
Traditional and some recently reported low power,high speed and high resolution approaches for SAR A/D converters are discussed.Based on SMIC 65 nm CMOS technology,two typical low power methods reported in previous wo...Traditional and some recently reported low power,high speed and high resolution approaches for SAR A/D converters are discussed.Based on SMIC 65 nm CMOS technology,two typical low power methods reported in previous works are validated by circuit design and simulation.Design challenges and considerations for high speed SAR A/D converters are presented.Moreover,an R–C combination based method is also addressed and a 10-bit SAR A/D converter with this approach is implemented in SMIC 90 nm CMOS process.The DNL and INL are measured to be less than 0.31 LSB and 0.59 LSB respectively.With an input frequency of 420 kHz at 1 MS/s sampling rate, the SFDR and ENOB are measured to be 67.6 dB and 9.46 bits respectively,and the power dissipation is measured to be just 3.17 mW.展开更多
文摘A compacted and low-offset low-power CMOS am- plifier for biosensor application is presented in this paper. It includes a low offset Op-Amp and a high precision current reference. With a novel continuous-time DC offset rejection scheme, the IC achieves lower offset voltage and lower power consumption compared to previous designs. This configuration rejects large DC offset and drift that exist at the skin-electrode interface without the need of external components. The proposed amplifier has been implemented in SMIC 0.18-μm 1P6M CMOS technol-ogy, with an active silicon area of 100 μm by 120 μm. The back-annotated simulation results demonstrated the circuit features the systematic offset voltage less than 80 μV, the offset drift about 0.27 μV/℃ for temperature ranging from –30℃ to 100℃ and the total power dissipation consumed as low as 37.8 μW from a 1.8 V single supply. It dedicated to monitor low amplitude biomedical signals recording.
基金supported by the National Natural Science Foundation of China (No. 61474081)Guangxi Key Laboratory of Precision Navigation Technology and Application, Guilin University of Electronic Technology (No. DH201513)
文摘A double photodiode(PD) constructed by p^+/N-well junction and N-well/p-sub junction was designed and fabricated in a UMC 0.18-lm CMOS process. Based on the device structure and mechanism of double PD, a novel small-signal equivalent circuit model considering the carrier transit effect and the parasitic RC time constant was presented. By this model with complete electronic components, the double PD can be incorporated in a commercial circuit simulator. The component values were extracted by fitting the measured S-parameters using simulated annealing algorithm, and a good agreement between the measurement and the simulation results was achieved.
基金supported by the National Natural Science Foundation of China(No.60676009)
文摘Traditional and some recently reported low power,high speed and high resolution approaches for SAR A/D converters are discussed.Based on SMIC 65 nm CMOS technology,two typical low power methods reported in previous works are validated by circuit design and simulation.Design challenges and considerations for high speed SAR A/D converters are presented.Moreover,an R–C combination based method is also addressed and a 10-bit SAR A/D converter with this approach is implemented in SMIC 90 nm CMOS process.The DNL and INL are measured to be less than 0.31 LSB and 0.59 LSB respectively.With an input frequency of 420 kHz at 1 MS/s sampling rate, the SFDR and ENOB are measured to be 67.6 dB and 9.46 bits respectively,and the power dissipation is measured to be just 3.17 mW.
