A new BPSK demodulator was presented.By using a clock multiplier with very simple circuit structure to replace the analog multiplier in the traditional BPSK demodulator,the circuit structure of the demodulator became ...A new BPSK demodulator was presented.By using a clock multiplier with very simple circuit structure to replace the analog multiplier in the traditional BPSK demodulator,the circuit structure of the demodulator became simpler and hence its power consumption became lower.Simpler structure and lower power will make the designed demodulator more suitable for use in an internal single chip design for a wireless implantable neural recording system.The proposed BPSK demodulator was implemented by Global Foundries 0.35μm CMOS technology with a 3.3 V power supply.The designed chip area is only 0.07 mm;and the power consumption is 0.5 mW.The test results show that it can work correctly.展开更多
基金Project supported by the National Natural Science Foundation of China(Nos.60976026,61076023)the National Basic Research Program of China(No.2011CB933203)the Fundamental Research Funds for the Central Universities,SCUT(No.2009ZM0196)
文摘A new BPSK demodulator was presented.By using a clock multiplier with very simple circuit structure to replace the analog multiplier in the traditional BPSK demodulator,the circuit structure of the demodulator became simpler and hence its power consumption became lower.Simpler structure and lower power will make the designed demodulator more suitable for use in an internal single chip design for a wireless implantable neural recording system.The proposed BPSK demodulator was implemented by Global Foundries 0.35μm CMOS technology with a 3.3 V power supply.The designed chip area is only 0.07 mm;and the power consumption is 0.5 mW.The test results show that it can work correctly.
