Novel Substrate pn Junction Isolation for RF Integrated Inductors on Silicon

A new method for reducing the substrate rated losses of integrated spiral inductors is presented.The method is to block the eddy currents induced by spiral inductors by directly forming pn junction isolation in the Si substrate. The substrate pn junction can be realized by using the standard silicon technologies without any additional processing steps.Integrated inductors on silicon are designed and fabricated. S parameters of the inductor based equivalent circuit are investigated and the inductor parameters are calculated.The impacts of the substrate pn junction isolation on the inductor quality factor are studied.The experimental results show that substrate pn junction isolation in certain depth has achieved a significant improvement.At 3GHz,the substrate pn junction isolation increases the inductor quality factor by 40%.

A Novel Lateral Solenoidal On-Chip Integrated Inductor Implemented in Conventional Si Process

A new structure of the on- chip integrated inductors im plem ented in conventional Si process is presented as a lateral solenoid.The fabrication process utilizes a conventional Si technology with standard double- layer m etal- lization.S param eters of the inductors based equivalent circuit are investigated and the inductor parameters are cal- culated from the m easured data.Experimental results are presented on an integrated inductors fabricated in a lateral solenoid type utilizing double m etal layers rather than a single metal layer as used in conventional planar spiral de- vices.Inductors with peak Q of 1.3and inductance value of 2 .2 n H are presented,which are com parable to conven- tional planar spiral inductors.

YIG Thin Film for RF Integrated Inductor

The yttrium iron garnet（YIG） thin films prepared by the sol-gel method and rapid thermal annealing（RTA） process for integrated inductor are investigated. The X-ray diffraction（XRD） results indicate that the YIG film annealed above 650 ℃ is poly-crystalline with single-phase garnet structure. Moreover, it can be found that the initial permeability μi, saturation magnetization MS and coercivity Hc of these YIG films increase with increasing RTA temperature. Low temperature annealing after crystallization can further improve the magnetic properties of YIG film. Thereby, a planar integrated inductor in the presence of Si substrate/SiO2 layer/Y2.8Bi0.2Fe5O12 thin film/Cu spiral coil structure is fabricated successfully by the standard IC processes. Due to the magnetic enhancement originated from YIG film, the inductance L and quality factor Q of the inductor with YIG film are improved in a certain frequency range.

A New Method for Optimizing Layout Parameter ofan Integrated On-Chip Inductor in CMOSRF IC's

Analyzing the influence on Q factor, which was caused by the parasitic effect in a CMOS RF on chip integrated inductor, a concise method to increase the Q factor has been obtained when optimizing the layout parameter. Using this method, the Q factor of 7.9 can be achieved in a 5nH inductor (operating frequency is 2GHz) while the errors in inductance are less than 0.5% compared with the aimed values. It is proved by experiments that this method can guarantee the sufficient accuracy but require less computation time. Therefore, it is of great use for the design of the inductor in CMOS RF IC’s.

Improving the quality factor of an RF spiral inductor with non-uniform metal width and non-uniform coil spacing

An improved inductor layout with non-uniform metal width and non-uniform spacing is proposed to increase the quality factor（Q factor）.For this inductor layout,from outer coil to inner coil,the metal width is reduced by an arithmetic-progression step,while the metal spacing is increased by a geometric-progression step. An improved layout with variable width and changed spacing is of benefit to the Q factor of RF spiral inductor improvement（approximately 42.86%）,mainly due to the suppression of eddy-current loss by weakening the current crowding effect in the center of the spiral inductor.In order to increase the Q factor further,for the novel inductor, a patterned ground shield is used with optimized layout together.The results indicate that,in the range of 0.5 to 16 GHz,the Q factor of the novel inductor is at an optimum,which improves by 67%more than conventional inductors with uniform geometry dimensions（equal width and equal spacing）,is enhanced by nearly 23%more than a PGS inductor with uniform geometry dimensions,and improves by almost 20%more than an inductor with an improved layout.

SVM strategy and analysis of a three-phase quasi-Z-source inverter with high voltage transmission ratio

Herein,we propose a novel three-phase quasi-Z-source inverter with a high voltage transmission ratio to address challenges such as high switching loss and sizeable magnetic components in the basic quasi-Z-source inverter.The proposed circuit topology,control strategy,and related analysis are presented.The circuit topology of the inverter comprises a quasi-Z-source network with an integrated magnetic inductor,an active clamp circuit,a three-phase inverter bridge,and an output LC filter,all of which are connected in series.An improved 12-sector space vector modulation scheme is proposed based on the root-mean-square value of the voltage and the instantaneous value of the current.Furthermore,analyses of the inverter voltage transmission ratio,resonant process,and parametric design guidelines for integrated magnetic inductor and zero-voltage switching conditions are presented.Experimental results on a 1-kVA prototype inverter demonstrate that the proposed inverter exhibits a higher transmission ratio and efficiency than existing inverters;thus,the proposed inverter would have broad prospects in low-voltage DC-AC applications.