Design of IP core based on AMBA bus

With the rapid development of integrated circuit(IC)technology,reusable intelligent property(IP)core design is widely valued by the industry.Based on the in-depth study of the functional characteristics of advanced microcontroller bus architecture(AMBA),a design scheme of IP core is presented,and it is divided into the functional modules,and the structural design of the IP core is completed.The relationship between the internal modules of the IP core is clarified,and the top-down design method is used to build the internal architecture of the IP core.The IP core interface module,register module,baud rate module,transmit module,receive module,and interrupt module are designed in detail by using Verilog language.The simulation results show that the designed IP core supports serial peripheral interface(SPI)protocol,the function coverage of IP core reaches 100%,the maximum working frequency reaches 200 MHz,and the resource occupancy rate is less than 15%.The reusable IP core can support multiple data formats,multiple timing transmission modes,and master/slave operation modes,reducing the resource consumption of hardware circuits and having stronger applicability.

Design of 4.25 Gbps Small Form-factor Pluggable(SFP) Transceiver

Compact, hot-pluggable, and data-agnostic, SFP modules bring up to 4.25 Gbps to a flexible new form factor. The SFP transceiver which is the core device of optical communication is always the research focus in the field of optical communication for both telecommunication and data communication applications. The working principles of SFP including the transmitter components, the receiver components and the microcontroller are discussed in detail. The basic theory of high-speed signal and the concept of high - speed circuit, high-speed board design techniques are presented. A new design of high performance, cost effective SFP transceiver and PCB layout are also presented. The performance of the transceiver is analyzed and the characteristics of the sample are coincident with the expected ones. The status of the transceiver can be monitored and controlled by F C bus through the interface in real time. This transceiver can meet the requirement of SFF-8472.

Circuit Implementation of Power Converter for High-Speed Switching Operations

Recently,high di/dt and dv/dt switching operations of power converter circuits has been discussed for realizing a high-efficiency power converter circuit.In this case,parasitic inductances of the bus bar between a DC capacitor and power devices may cause issues of overshoot voltage and electromagnetic interference(EMI)noise.Therefore,it is necessary to design the bus bar geometry while considering the minimization and optimization of the parasitic inductance of bus bar.This paper discusses a relationship between bus bar geometry and switching characteristics.In addition,the bus bar analysis is based on the PEEC method,and the bus bar geometry is designed by considering the stray inductance with using an inductance-map method.Moreover,this paper also presents a design procedure of acceptable stray inductance based on a standardization method.It should be noted that the stray inductance is designed not for minimization,but optimization,and it is shown not as an absolute value(H),but as a percentage value(%).Finally,the oscillation waveforms under turn-off operation will be discussed depending on the bus bar geometry.

Design and implementation of high-speed real-time data acquisition system based on FPGA

The electromagnetic radiation will result in informa- tion leakage being recovered when computers work. This article presents a high-speed real-time data acquisition system based on peripheral component interconnect （PCI） bus and field programmable gate array （FPGA） for sampling electromagnetic radiation caused by video signal. The hardware design and controlling flow of each module are introduced in detail. The sampling rate can reach 64 Msps and system transfers speed can be up to 128 Mb/s by using time interleaving, which increases the overall sampling speed of a system by operating two data converters in parallel.