FORWARD GATED-DIODE METHOD FOR DIRECTLY MEASURING STRESS-INDUCED INTERFACE TRAPS IN NMOSFET/SOI

Forward gated-diode Recombination-Generation(R-G) current method is applied to an NMOSFET/SOI to measure the stress-induced interface traps in this letter. This easy but accurate experimental method can directly give stress-induced average interface traps for characterizing the device’s hot carrier characteristics. For the tested device, an expected power law relationship of △Nit-t0.787 between pure stress-induced interface traps and accumulated stressing time is obtained.

FORWARD GATED-DIODE METHOD FOR EXTRACTING HOT-CARRIER-STRESS-INDUCED BACK INTERFACE TRAPS IN SOI/NMOSFETs

The forward gated-diode R-G current method for extracting the hot-carrier-stress-induced back interface traps in SOI/NMOSFET devices has been demonstrated in this letter. This easy and accurate experimental method directly gives the induced interface trap density from the measured R-G current peak of the gated-diode architecture. An expected power law relationship between the induced back interface trap density and the accumulated stress time has been obtained.

Numerical Analysis of Characterized Back Interface Trapsof SOI Devices by R-G Current

Characterized back interface traps of SOI devices by the Recombination\|Generation (R\|G) current has been analyzed numerically with an advanced semiconductor simulation tool,namely DESSIS\|ISE.The basis of the principle for the R\|G current’s characterizing the back interface traps of SOI lateral p\++p\+-n\++ diode has been demonstrated.The dependence of R\|G current on interface trap characteristics has been examined,such as the state density,surface recombination velocity and the trap energy level.The R\|G current proves to be an effective tool for monitoring the back interface of SOI devices.

Effects of stress conditions on the generation of negative bias temperature instability-associated interface traps

The exponent n of the generation of an interface trap （Nit）, which contributes to the power-law negative bias temperature instability （NBTI） degradation, and the exponent’s time evolution are investigated by simulations with varying the stress voltage Vg and temperature T. It is found that the exponent n in the diffusion-limited phase of the degradation process is irrelevant to both Vg and T. The time evolution of the exponent n is affected by the stress conditions, which is reflected in the shift of the onset of the diffusion-limited phase. According to the diffusion profiles, the generation of the atomic hydrogen species, which is equal to the buildup of Nit, is strongly correlated with the stress conditions, whereas the diffusion of the hydrogen species shows Vg-unaffected but T-affected relations through the normalized results.

New Forward Gated-Diode Technique for Separating Front Gate Interface- from Oxide-Traps Induced by Hot-Carrier-Stress in SOI-NMOSFETs

The front gate interface and oxide traps induced by hot carrier stress in SOI NMOSFETs are studied.Based on a new forward gated diode technique,the R G current originating from the front interface traps is measured,and then the densities of the interface and oxide traps are separated independently.The experimental results show that the hot carrier stress of front channel not only results in the strong generation of the front interface traps,but also in the significant oxide traps.These two kinds of traps have similar characteristic in increasing with the hot carrier stress time.This analysis allows one to obtain a clear physical picture of the effects of the hot carrier stress on the generating of interface and oxide traps,which help to understand the degradation and reliability of the SOI MOSFETs.

Effects of wet-ROA on shallow interface traps of n-type 4H-SiC MOS capacitors

The effects of wet re-oxidation annealing （wet-ROA） on the shallow interface traps of n-type 4H-SiC metal oxide-semiconductor （MOS） capacitors were investigated by Gray-Brown method and angle-dependent X- ray photoelectron spectroscopy technique. The results present the energy distribution of the density of interface traps （Dit） from 0 to 0.2 eV below SiC conduction band edge （Ec） of the sample with wet-ROA for the first time, and indicate that wet-ROA could reduce the Dit in this energy range by more than 60%. The reduction in Dit is attributed to the reaction between the introduced oxygen and the SiOxCy species, which results in C release and SiOxCy transformation into higher oxidation states, thus reducing the SiOxCy content and the SiOxCy interface transition region thickness.

Incomplete charge transfer in CMOS image sensor caused by Si/SiO_(2)interface states in the TG channel

CMOS image sensors produced by the existing CMOS manufacturing process usually have difficulty achieving complete charge transfer owing to the introduction of potential barriers or Si/SiO_(2)interface state traps in the charge transfer path,which reduces the charge transfer efficiency and image quality.Until now,scholars have only considered mechanisms that limit charge transfer from the perspectives of potential barriers and spill back effect under high illumination condition.However,the existing models have thus far ignored the charge transfer limitation due to Si/SiO_(2)interface state traps in the transfer gate channel,particularly under low illumination.Therefore,this paper proposes,for the first time,an analytical model for quantifying the incomplete charge transfer caused by Si/SiO_(2)interface state traps in the transfer gate channel under low illumination.This model can predict the variation rules of the number of untransferred charges and charge transfer efficiency when the trap energy level follows Gaussian distribution,exponential distribution and measured distribution.The model was verified with technology computer-aided design simulations,and the results showed that the simulation results exhibit the consistency with the proposed model.

Physical insights into trapping effects on vertical GaN-on-Si trench MOSFETs from TCAD

Vertical GaN power MOSFET is a novel technology that offers great potential for power switching applications.Being still in an early development phase,vertical GaN devices are yet to be fully optimized and require careful studies to foster their development.In this work,we report on the physical insights into device performance improvements obtained during the development of vertical GaN-on-Si trench MOSFETs(TMOS’s)provided by TCAD simulations,enhancing the dependability of the adopted process optimization approaches.Specifically,two different TMOS devices are compared in terms of transfer-curve hysteresis(H)and subthreshold slope(SS),showing a≈75%H reduction along with a≈30%SS decrease.Simulations allow attributing the achieved improvements to a decrease in the border and interface traps,respectively.A sensitivity analysis is also carried out,allowing to quantify the additional trap density reduction required to minimize both figures of merit.

Interface and border trapping effects in normally-off Al2O3/AlGaN/GaN MOS-HEMTs with different post-etch surface treatments

Trapping effect in normally-off Al2O3/AlGaN/GaN metal–oxide–semiconductor (MOS) high-electron-mobility transistors (MOS-HEMTs) with post-etch surface treatment was studied in this paper. Diffusion-controlled interface oxidation treatment and wet etch process were adopted to improve the interface quality of MOS-HEMTs. With capacitance–voltage (C–V) measurement, the density of interface and border traps were calculated to be 1.13 × 10^12 cm^−2 and 6.35 × 10^12 cm^−2, effectively reduced by 27% and 14% compared to controlled devices, respectively. Furthermore, the state density distribution of border traps with large activation energy was analyzed using photo-assisted C–V measurement. It is found that irradiation of monochromatic light results in negative shift of C–V curves, which indicates the electron emission process from border traps. The experimental results reveals that the major border traps have an activation energy about 3.29 eV and the change of post-etch surface treatment process has little effect on this major activation energy.

Energy Dependence of Interface Trap Density——Investigated by Relaxation Spectral Technique

According to the definition of interface traps,a new application of relaxation spectral technique to sub-threshold swing shift and sub-threshold gate voltage shift is proposed to extract interface trap density in 1.9nm MOSFET.And thus the energy distribution of interface trap can be determined.According to the two methods,the energy profile of interface traps agrees with those reported in literature.Compared to other methods,this method is simpler and more convenient.

Improved electrical properties of NO-nitrided SiC/SiO2 interface after electron irradiation

Effective improvement in electrical properties of NO passivated SiC/SiO2 interface after being irradiated by electrons is demonstrated.The density of interface traps after being irradiated by 100-kGy electrons decreases by about one order of magnitude,specifically,from 3×1012 cm-2·eV-1 to 4×1011 cm-2·eV-1 at 0.2 eV below the conduction band of 4H-SiC without any degradation of electric breakdown field.Particularly,the results of x-ray photoelectron spectroscopy measurement show that the C-N bonds are generated near the interface after electron irradiation,indicating that the carbon-related defects are further reduced.

A Method to Separate Effects of Oxide-Trapped Charge and Interface-Trapped Charge on Threshold Voltage in pMOSFETs Under Hot-Carrier Stress

A simple new method based on the measurement of charge pumping technique is proposed to separate and quantify experimentally the effects of oxide-trapped charges and interface-trapped charges on threshold voltage degradation in p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) under hot-carrier stress.Further,the experimental results verify the validness of this method.It is shown that,all three mechanisms of electron trapping effect,hole trapping effect and interface trap generation play important roles in p-channel MOSFETs degradation.It is noted that interface-trapped charge is still the dominant mechanism for hot-carrier-induced degradation in p-channel MOSFETs,while a significant contribution of oxide-trapped charge to threshold voltage is demonstrated and quantified.

Two-dimensional analysis of the interface state effect on current gain for a 4H-SiC bipolar junction transistor

This paper studies two-dimensional analysis of the surface state effect on current gain for a 4H-SiC bipolar junction transistor （BJT）. Simulation results indicate the mechanism of current gain degradation, which is surface Fermi level pinning leading to a strong downward bending of the energy bands to form the channel of surface electron recombination current. The experimental results are well-matched with the simulation, which is modeled by exponential distributions of the interface state density replacing the single interface state trap. Furthermore, the simulation reveals that the oxide quality of the base emitter junction interface is very important for 4H-SiC BJT performance.

Enhanced interface properties of diamond MOSFETs with Al2O3 gate dielectric deposited via ALD at a high temperature

The interface state of hydrogen-terminated(C-H)diamond metal-oxide-semiconductor field-effect transistor(MOSFET)is critical for device performance.In this paper,we investigate the fixed charges and interface trap states in C-H diamond MOSFETs by using different gate dielectric processes.The devices use Al_(2)O_(3) as gate dielectrics that are deposited via atomic layer deposition(ALD)at 80℃and 300℃,respectively,and their C-V and I-V characteristics are comparatively investigated.Mott-Schottky plots(1/C2-VG)suggest that positive and negative fixed charges with low density of about 10^(11)cm^(-2) are located in the 80-℃-and 300-℃deposition Al2O3 films,respectively.The analyses of direct current(DC)/pulsed I-V and frequency-dependent conductance show that the shallow interface traps(0.46 eV-0.52 eV and 0.53 eV-0.56 eV above the valence band of diamond for the 80-℃and 300-℃deposition conditions,respectively)with distinct density(7.8×10^(13)eV^(-1)·cm^(-2)-8.5×10^(13)eV^(-1)·cm^(-2) and 2.2×10^(13)eV^(-1)·cm^(-2)-5.1×10^(13)eV^(-1)·cm^(-2) for the 80-℃-and 300-℃-deposition conditions,respectively)are present at the Al2O3/C-H diamond interface.Dynamic pulsed I-V and capacitance dispersion results indicate that the ALD Al_(2)O_(3) technique with 300-℃deposition temperature has higher stability for C-H diamond MOSFETs.

Effect of NO annealing on charge traps in oxide insulator and transition layer for 4H-SiC metal–oxide–semiconductor devices

The effect of nitric oxide（NO） annealing on charge traps in the oxide insulator and transition layer in n-type4H–Si C metal–oxide–semiconductor（MOS） devices has been investigated using the time-dependent bias stress（TDBS）,capacitance–voltage（C–V）,and secondary ion mass spectroscopy（SIMS）.It is revealed that two main categories of charge traps,near interface oxide traps（Nniot） and oxide traps（Not）,have different responses to the TDBS and C–V characteristics in NO-annealed and Ar-annealed samples.The Nniotare mainly responsible for the hysteresis occurring in the bidirectional C–V characteristics,which are very close to the semiconductor interface and can readily exchange charges with the inner semiconductor.However,Not is mainly responsible for the TDBS induced C–V shifts.Electrons tunneling into the Not are hardly released quickly when suffering TDBS,resulting in the problem of the threshold voltage stability.Compared with the Ar-annealed sample,Nniotcan be significantly suppressed by the NO annealing,but there is little improvement of Not.SIMS results demonstrate that the Nniotare distributed within the transition layer,which correlated with the existence of the excess silicon.During the NO annealing process,the excess Si atoms incorporate into nitrogen in the transition layer,allowing better relaxation of the interface strain and effectively reducing the width of the transition layer and the density of Nniot.

Impact of nitrogen plasma passivation on the interface of germanium MOS capacitor

Nitrogen plasma passivation （NPP） on （111） germanium （Ge） was studied in terms of the interface trap density, roughness, and interfacial layer thickness using plasma-enhanced chemical vapor deposition （PECVD）. The results show that NPP not only reduces the interface states, but also improves the surface roughness of Ge, which is beneficial for suppressing the channel scattering at both low and high field regions of Ge MOSFETs. However, the interracial layer thickness is also increased by the NPP treatment, which will impact the equivalent oxide thickness （EOT） scaling and thus degrade the device performance gain from the improvement of the surface morphology and the interface passivation. To obtain better device performance of Ge MOSFETs, suppressing the interfacial layer regrowth as well as a trade-off with reducing the interface states and roughness should be considered carefully when using the NPP process.

Modeling of tunneling current in ultrathin MOS structure with interface trap charge and fixed oxide charge

A model based on analysis of the self-consistent Poisson-Schrodinger equation is proposed to investigate the tunneling current of electrons in the inversion layer of a p-type metal-oxide-semiconductor （MOS） structure. In this model, the influences of interface trap charge （ITC） at the Si-SiO2 interface and fixed oxide charge （FOC） in the oxide region are taken into account, and one-band effective mass approximation is used. The tunneling probability is obtained by employing the transfer matrix method. Further, the effects of in-plane momentum on the quantization in the electron motion perpendicular to the Si-SiO2 interface of a MOS device are investigated. Theoretical simulation results indicate that both ITC and FOC have great influence on the tunneling current through a MOS structure when their densities are larger than l012 cm 2, which results from the great change of bound electrons near the Si-SiO2 interface and the oxide region. Therefore, for real ultrathin MOS structures with ITC and FOC, this model can give a more accurate description for the tunneling current in the inversion layer.

Interface states in Al_2O_3/AlGaN/GaN metal-oxide-semiconductor structure by frequency dependent conductance technique

Frequency dependent conductance measurements are implemented to investigate the interface states in Al2O3/A1GaN/GaN metal-oxide-semiconductor （MOS） structures. Two types of device structures, namely, the recessed gate structure （RGS） and the normal gate structure （NGS）, are studied in the experiment. Interface trap parameters includ-ing trap density Dit, trap time constant ιit, and trap state energy ET in both devices have been determined. Furthermore, the obtained results demonstrate that the gate recess process can induce extra traps with shallower energy levels at the Al2O3/AlGaN interface due to the damage on the surface of the AlGaN barrier layer resulting from reactive ion etching （RIE）.

High-Pressure Oxidation on Ge:Improvement of Ge/GeO2 Interface and GeO2 Bulk Properties

On the basis of thermodynamic and kinetic consideration of Ge-O system,high-pressure oxidation(HPO)on Ge was proposed to suppress the GeO desorption during the thermal oxidation and significant improvements of Ge/GeO2-based gate stacks have been achieved.It is found that the post oxidation annealing at lower temperatures is helpful to passivate the interface defects at the Ge/GeO2 stack generated by the conventional thermal oxidation,while the high-quality GeO2 bulk properties can only be achieved by HPO that grows GeO2 film at high temperatures without the GeO desorption.This paper reviews the advantage of HPO on the formation of Ge/GeO2 stacks in terms of Ge/GeO2 interface and GeO2 bulk properties.

Research of Trap and Electron Density Distributions in the Interface of Polyimide/Al2O3 Nanocomposite Films Based on IDC and SAXS

The distributions of traps and electron density in the interfaces between polyimide （PI） matrix and Al2O3 nanoparticles are researched using the isothermal decay current and the small-angle x-ray scattering （SAXS） tests. According to the electron density distribution for quasi two-phase mixture doped by spherical nanoparticles, the electron densities in the interfaces of PI/Al2O3 nanocomposite films are evaluated. The trap level density and carrier mobility in the interface are studied. The experimental results show that the distribution and the change rate of the electron density in the three layers of interface are different, indicating different trap distributions in the interface layers. There is a maximum trap level density in the second layer, where the maximum trap level density for the nanocomposite film doped by 25 wt% is 1.054 × 10^22 eV·m^-3 at 1.324eV, resulting in the carrier mobility reducing. In addition, both the thickness and the electron density of the nanocomposite film interface increase with the addition of the doped Al2O3 contents. Through the study on the trap level distribution in the interface, it is possible to further analyze the insulation mechanism and to improve the performance of nano-dielectric materials.